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Test Flow Selection...
Test Flow Selection for Stacked Integrated Circuits
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- SenGupta, Breeta (författare)
- Lund University,Lunds universitet,Institutionen för elektro- och informationsteknik,Institutioner vid LTH,Lunds Tekniska Högskola,Department of Electrical and Information Technology,Departments at LTH,Faculty of Engineering, LTH,Lund Univ, Sweden
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- Nikolov, Dimitar (författare)
- Lund University,Lunds universitet,Integrerade elektroniksystem,Forskargrupper vid Lunds universitet,Integrated Electronic Systems,Lund University Research Groups,Lund Univ, Sweden
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- Dash, Assmitra (författare)
- Linköpings universitet,Linköping University
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visa fler...
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- Larsson, Erik (författare)
- Lund University,Lunds universitet,Integrerade elektroniksystem,Forskargrupper vid Lunds universitet,Integrated Electronic Systems,Lund University Research Groups,Lund Univ, Sweden
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visa färre...
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(creator_code:org_t)
- 2019-08-14
- 2019
- Engelska.
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Ingår i: Journal of Electronic Testing: Theory and Applications. - : Springer Science and Business Media LLC. - 0923-8174 .- 1573-0727. ; 35:4, s. 425-440
- Relaterad länk:
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http://dx.doi.org/10... (free)
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https://link.springe...
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https://lup.lub.lu.s...
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https://doi.org/10.1...
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https://urn.kb.se/re...
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Abstract
Ämnesord
Stäng
- Integrated circuits (ICs) with a single chip (die) are typically tested with a test flow consisting of two test instances: (1) wafer sort for the bare chip and (2) package test for the packaged IC. For ICs with stacked chips - 3D Stacked ICs - there are many possible test instances, even more test flows, and no commonly used test flow. In this paper, we propose a test flow selection algorithm (TFSA) to obtain a test flow for a given 3D Stacked IC. The TFSA results in a test flow for a given 3D Stacked IC, such that the expected total test time to produce each good package is minimized. We implemented the TFSA, three straightforward test flow schemes and an exhaustive search, and experimentally compared the test flow schemes on three different test architecture design approaches. The results demonstrate the importance to have methods both to select the test flow and design the test architecture.
Ämnesord
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik -- Datorsystem (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering -- Computer Systems (hsv//eng)
- NATURVETENSKAP -- Data- och informationsvetenskap -- Datavetenskap (hsv//swe)
- NATURAL SCIENCES -- Computer and Information Sciences -- Computer Sciences (hsv//eng)
Nyckelord
- 3D IC
- Effective yield
- Expected time
- IEEE 1500
- Quantity
- Stacked integrated circuits
- Test architecture
- Test flow
- Test plan
- Test time
- Yield
- 3D IC; Stacked integrated circuits; Test flow; Test time; Yield; Test plan; IEEE 1500; Test architecture; Expected time; Effective yield; Quantity
Publikations- och innehållstyp
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- ref (ämneskategori)
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