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31.
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33.
  • Deb, Abhijit Kumar, et al. (författare)
  • System design for DSP applications in transaction level modeling paradigm
  • 2004
  • Ingår i: 41st Design Automation Conference, Proceedings 2004. - New York, NY, USA : ACM. - 1581138288 ; , s. 466-471
  • Konferensbidrag (refereegranskat)abstract
    • In this paper, we systematically define three transaction level models (TLMs), which reside at different levels of abstraction between the functional and the implementation model of a DSP system. We also show a unique language support to build the TLMs. Our results show that the abstract TLMs can be built and simulated much faster than the implementation model at the expense of a reasonable amount of simulation accuracy.
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34.
  • Deb, Abhijit Kumar, et al. (författare)
  • System design for DSP applications using the MASIC methodology
  • 2004
  • Ingår i: DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS. - LOS ALAMITOS : IEEE COMPUTER SOC. - 0769520855 ; , s. 630-635
  • Konferensbidrag (refereegranskat)abstract
    • Expensive top-down iterations are often required in the design cycle of complex DSP systems. In this paper, we introduce two levels of abstraction in the design flow by, systematically categorizing the architectural decisions. As a result, the top-down iteration loop is broken. We also present a technique to capture and inject the architectural decisions such that the system models can be created and simulated efficiently. The concepts are illustrated by a realistic speech processing example, which is implemented using the AMBA on-chip architecture. Our methodology offers a smooth path from the functional modeling phase to the implementation level, facilitates the reuse of HW and SW components, and enjoys existing tool support at the backend.
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35.
  • Deivasigamani, M., et al. (författare)
  • Concept and design of exhaustive-parallel search algorithm for Network-on-Chip
  • 2011
  • Ingår i: Int. Syst. Chip Conf.. - 9781457716164 ; , s. 150-155
  • Konferensbidrag (refereegranskat)abstract
    • This paper presents the concept and design of exhaustive-parallel search algorithm for Network-on-Chip. The proposed parallel algorithm searches minimal path between source and destination in a forward-wave-propagation manner. The algorithm guarantees setup latency if the setup path exists. A high performance switch is designed to support exhaustive-parallel search algorithm. The NoC fabric is designed for 88 mesh architecture and its performance is evaluated.
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37.
  • Ebrahimi, Masoumeh, et al. (författare)
  • Rescuing healthy cores against disabled routers
  • 2014
  • Konferensbidrag (refereegranskat)abstract
    • A router may be temporarily or permanently disabled in NoCs for several reasons such as saving power, occurring faults or testing. Disabling a router, however, may have a severe impact on the performance or functionality of the entire system if it results in disconnecting the core from the network. In this paper, we propose a deadlock-free routing algorithm which allows the core to stay connected to the system and continue its normal operation when its connected router is disabled. Our analysis and experiments show that the proposed technique has 100%, 93.60%, and 87.19% network availability by 100% packet delivery when 1, 2 and 3 routers are defunct or intentionally disabled. The algorithm provides adaptivity and it is lightweight, requiring one and two virtual channels along the X and Y dimension, respectively.
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38.
  • Ejaz, Ahsen, et al. (författare)
  • Costs and benefits of flexibility in spatial division Circuit Switched Networks-on-Chip
  • 2013
  • Ingår i: NoCArc '13 Proceedings of the Sixth International Workshop on Network on Chip Architectures. - New York, NY, USA : Association for Computing Machinery (ACM). - 9781450323703 ; , s. 41-46
  • Konferensbidrag (refereegranskat)abstract
    • Although most Network-on-Chip (NoC) designs are based on Packet Switching (PS), the importance of Circuit Switching (CS) should not be underestimated. Many MPSoC executing real-time applications require an underlying communication backbone that can relay messages from one node to another with guaranteed throughput. Compared to PS, CS can provide guaranteed throughput with lower area and power overheads. It is also highly suited for applications where nodes transfer long messages. Spatial Division Multiplexing (SDM) can allow more efficient use of available network resources by dividing them among multiple simultaneous transactions. The network developed by Vali [1] has three design variations based on the number of sub-channels, has a predictable connection setup time, and uses CS to provide guaranteed throughput once a connection is established. In this paper we use this network as a basis to study the effect of flexibility based on SDM, on the performance of a CS networks. A network evaluation platform has been developed to configure and evaluate networks with a maximum of 8 sub-networks, with each sub-network comprising of 1, 2 or 4 sub-channels. We show that under uniform traffic pattern with requests of uniform random bandwidth (BW) requirement, a less flexible network outperforms a network with higher flexibility due to a phenomenon we call 'stray requests'. We conclude this paper by showing that under high network traffic, performance of our flexible networks can be as much as 113% better than HAGAR [2] and Liu's [3] network. Co
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