| 91. |
- She, Huimin, et al.
(author)
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Traffic splitting with network calculus for mesh sensor networks
- 2007
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In: Proceedings of Future Generation Communication and Networking, FGCN 2007. - : IEEE Computer Society. - 9780769530482 ; , s. 371-376
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Conference paper (peer-reviewed)abstract
- In many applications of sensor networks, it is essential to ensure that messages are transmitted to their destinations as early as possible and the buffer size of each sensor node is as small as possible. In this paper, we firstly propose a mesh sensor network system model. Based on this system model, the expressions for deriving the delay bound and buffer requirement bound are presented using network calculus. In order to balance traffic load and improve resource utilization, three traffic splitting mechanisms are proposed The numerical results show that the delay bound and buffer requirement bound are lowered while applying those traffic splitting mechanisms. And thus the performance of the whole sensor network is improved.
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| 92. |
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| 93. |
- Thid, Rikard, et al.
(author)
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Flexible bus and NoC performance analysis with configurable synthetic workloads
- 2006
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In: DSD 2006. - 0769526098 ; , s. 681-688
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Conference paper (peer-reviewed)abstract
- We present a flexible method for bus and network on chip performance analysis, which is based on the adaptation of workload models to resemble various applications. Our analysis method assists in the selection of a communication infrastructure early in the design process. The method uses (1) synthetic workload models which are similar to timed Petri nets and (2) the b-model for self-similar workloads. This allows the exploration of larger portions of the design space than possible with traditional stochastic models. The method is illustrated with tutorial examples where both a No C and a bus based platform are analyzed.
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| 94. |
- Vitkovski, A., et al.
(author)
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Low-power and error protection coding for network-on-chip traffic
- 2008
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In: IET Computers and Digital Techniques. - : Institution of Engineering and Technology (IET). - 1751-8601. ; 2:6, s. 483-492
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Journal article (peer-reviewed)abstract
- The power consumption of the network-on-chip communication backbone is explored and the effectiveness of low-power encoding and error protection techniques is analysed. For the switch under the study, a Nostrum defective routing switch, simulations and power analysis suggest that only a minor fraction of the power is dissipated in the logic blocks, whereas the major part is due to the interconnection wires. The authors have investigated a number of low-power and data protection mechanisms and studied their impact on power consumption of the whole network. The bus-invert encoding scheme and a limited set of Hamming data protection codes have been implemented on both data link and at the network layer. However, it turned out that all low-power data encoding schemes have little potential to decrease power consumption due to the significant overhead. On the other hand, error protection mechanisms have a significant potential to decrease power consumption because they allow to operate the network at a lower voltage. The authors' experiments show a 20% decrease of power consumption for a given error rate and for a given performance.
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| 95. |
- Wang, Qiang, et al.
(author)
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Hardware/Software Co-design of an ATCA-based Computation Platform for Data Acquisition and Triggering
- 2009
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In: 16th IEEE NPSS Real Time Conference. - 9781424457960 ; , s. 485-489
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Conference paper (peer-reviewed)abstract
- An ATCA-based computation platform for data acquisition and trigger(TDAQ) applications has been developed for multiple future projects such its PANDA. HADES, and BESIII. Each Compute Node (CN) appears as one (if the fourteen Field Replaceable Units (FRU) in an ATCA shelf, which in total features a high performance of 1890 Clips inter-FPGA on-board channels, 1456 Gbps inter-board backplane connections, 728 Gbps full-duplex optical links, 70 Gbps Ethernet. 140 GBytes DDR2 SDRAM. and all computing resources of 70 Xilinx Virtex-4 FX60 FPGAs. Corresponding to (the system architecture, a hardware/software co-design approach is proposed to ease and accelerate the development for different experiments. In the uniform system design. application-specific computation is to be implemented as customized hardware co-processors, while the embedded PowerPC processor takes charge of flexible slow controls and transmission protocol processing.
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| 96. |
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| 97. |
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| 98. |
- Weixing, W., et al.
(author)
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An algorithm for electing cluster heads based on maximum residual energy
- 2006
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In: IWCMC Proc. Int. Wireless Com. Mob. Comput. Conf.. - New York, NY, USA : ACM. - 1595933069 - 9781595933065 ; , s. 1465-1470
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Conference paper (peer-reviewed)abstract
- One of the main challenges in wireless sensor networks is to obtain long system lifetime. We propose an algorithm for electing the cluster head node based on the maximum residual energy for the purpose of even distribution of energy consumption in the overall network and obtaining the longest network lifetime. To maintain the original performance of the network, the lifetime is suggested to be expressed as to both the maximum last node dying time and the minimum time difference between the last node dying and the first node dying. The key parameter - the electing coefficient (θ) was obtained and evaluated. The optimal θ value is related to number of nodes, energy consumption of cluster members (ECCM), and energy consumption of the cluster head (ECCH). θ descends when number of nodes and ECCM decrease, and when EUCH increases. However, when energy consumptions of the cluster head and cluster members change proportionally, θ seems to be affected slightly. Results show that network lifetime can be prolonged when cluster heads are elected with the optimal θ value.
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| 99. |
- Weldezion, Awet Yemane, et al.
(author)
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Scalability of Network-on-Chip Communication Architecture for 3-D Meshes
- 2009
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In: 2009 3RD ACM/IEEE INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP. - NEW YORK : IEEE. - 9781424441426 ; , s. 114-123
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Conference paper (peer-reviewed)abstract
- Design Constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3-D chip stacks an enticing technology solution for massively integrated electronic systems. The scarcity of vertical interconnects however imposes special constraints on the design of the communication architecture. This article examines the performance and scalability of different communication topologiesfor 3-D Network-on-Chips (NoC) using Through-Silicon-Was (TSV) for inter-die connectivity. Cycle accurate RTL-level simulations are conducted for two communication schemes based on a 7-port switch and a centrally arbitrated vertical bus using different traffic patterns. The scalability of the 3-D NoC is examined under both communication architectures and compared to 2-D NoC structures in terms of throughput and latency in order to quantify the variation of network performance with the number of nodes and derive key design guidelines.
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| 100. |
- Wolf, Pieter van der, et al.
(author)
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Definition of Device Level Interface with QoS : Draft Specification
- 2007
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Reports (other academic/artistic)abstract
- The extensions to standard IP communication interfaces proposed in SPRINT WP3document D3.1 are defined. Flow identification signals are added to the DLI signal level interface so transactionscan indicate the services they require. These services are specified as Contracts thatdefine the flow characteristics required for correct operation. These characteristics arethe main input to an analysis method to validate that a SoC design achieves its performance targets. DLI-Guard units are defined that enforce Contracts by regulating an IP module’s identified flows. Monitoring of flow characteristics, such as latency, is also optionally provided. A configuration API for DLI-Guards is outlined together with example code toillustrate its use. This specification is successfully applied to AMBA AXI, the prime example DLI
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