| 1. |
- Collin, Mikael, et al.
(författare)
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A performance and energy exploration of dictionary code compression architectures
- 2011
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Ingår i: 2011 International Green Computing Conference and Workshops (IGCC). - : IEEE conference proceedings. - 9781457712227 ; , s. 1-8
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Konferensbidrag (refereegranskat)abstract
- We have made a performance and energy exploration of a previously proposed dictionary code compression mechanism where frequently executed individual instructions and/or sequences are replaced in memory with short code words. Our simulated design shows a dramatically reduced instruction memory access frequency leading to a performance improvement for small instruction cache sizes and to significantly reduced energy consumption in the instruction fetch path. We have evaluated the performance and energy implications of three architectural parameters: branch prediction accuracy, instruction cache size and organization. To asses the complexity of the design we have implemented the critical stages in VHDL.
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| 2. |
- Mand, Nowshad Painda, et al.
(författare)
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Artificial neural network emulation on NOC based multi-core FPGA platform
- 2012
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Ingår i: NORCHIP, 2012. - : IEEE. - 9781467322218 ; , s. 6403122-
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Konferensbidrag (refereegranskat)abstract
- With the emergence of Multi-Core platforms, brain emulation in the form of Artificial Neural Nets has been announced as one of the important key research area. However, due to large non-linear growth of inter-neuron connectivity, direct mapping of ANNs to silicon structures is very difficult due to communication bottleneck.
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| 3. |
- Navas, Byron, et al.
(författare)
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The RecoBlock SoC Platform : A Flexible Array of Reusable Run-Time-Reconfigurable IP-Blocks
- 2013
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Ingår i: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013. - 9781467350716 ; , s. 833-838
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Konferensbidrag (refereegranskat)abstract
- Run-time reconfigurable (RTR) FPGAs combine the flexibility of software with the high efficiency of hardware. Still, their potential cannot be fully exploited due to increased complexity of the design process. Consequently, to enable an efficient design flow, we devise a set of prerequisites to increase the flexibility and reusability of current FPGA-based RTR architectures. We apply these principles to design and implement the RecoBlock SoC platform, which main characterization is (1) a RTR plug-and-play IP-Core whose functionality is configured at run-time; (2) flexible inter-block communication configured via software, and (3) built-in buffers to support data-driven streams and inter-process communications. We illustrate the potential of our platform by a tutorial case study using an adaptive streaming application to investigate different combinations of reconfigurable arrays and schedules. The experiments underline the benefits of the platform and shows resource utilization.
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| 4. |
- Navas, Byron, et al.
(författare)
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Towards the generic reconfigurable accelerator : Algorithm development, core design, and performance analysis
- 2013
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Konferensbidrag (refereegranskat)abstract
- Adoption of reconfigurable computing is limited in part by the lack of simplified, economic, and reusable solutions. The significant speedup and energy saving can increase performance but also design complexity; in particular for heterogeneous SoCs blending several CPUs, GPUs, and FPGA-Accelerator Cores. On the other hand, implementing complex algorithms in hardware requires modeling and verification, not only HDL generation. Most approaches are too specific without looking for reusability. Therefore, we present a solution based on: (1) a design methodology to develop algorithms accelerated in reconfigurable/non-reconfigurable IP-Cores, using common access tools, and contemplating verification from model to embedded software stages; (2) a generic accelerator core design that enables relocation and reuse almost independently of the algorithm, and data-flow driven execution models; and (3) a performance analysis of the acceleration mechanisms included in our system (i.e., accelerator core, burst I/O transfers, and reconfiguration pre-fetch). In consequence, the implemented system accelerates algorithms (e.g., FIR and Kalman filters) with speedups up to 3 orders of magnitude, compared to processor implementations.
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| 5. |
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| 6. |
- Uddin, Saif, et al.
(författare)
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An improved transmission scheme for error-prone inter-chip Network-on-Chip communication links implemented on FPGAs
- 2013
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Ingår i: 10th FPGAworld Conference - Academic Proceedings 2013, FPGAworld 2013. - New York, NY, USA : ACM. - 9781450324960
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Konferensbidrag (refereegranskat)abstract
- Network-on-Chip (NoC) is an alternative to traditional busses for faster interconnect mechanism. The aim is to have infinite scalability, and this implies the possibility to extend the on-chip NoC communication protocol off-chip. To gain wholesome advantage of Network-on-Chip (NoC), off-chip extensions should also have similar communication throughput compared to the on-chip network. Faster data-rate is the single most demanded requirement of modern applications. There is a continuous drive to fulfill this escalating demand as much as possible. Two of the most prominent limiting factors in achieving this purpose are 'reduced accuracy' and 'protocol handling', especially in case of systems which do not have synchronous communication. Efficient optimizations are needed in multiple areas to upgrade the speed of data transfer. This paper presents an improved off-chip network solution to a slower and error-prone board-bridge part of a Network-on-Chip (NoC). The new solution increases the accuracy and speed of the plesiochronous off-chip extension to the NoC. The Network-on-Chip has 16 processor-nodes implemented on four interconnected plesiochronous Altera Stratix-II FPGA boards in 4x4 configuration in such a way that each board hosts a Quad-core NoC.
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| 7. |
- Uddin, Saif, et al.
(författare)
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Testing of an off-chip NoC protocol using a BIST/Synthesizable Testbench approach
- 2012
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Ingår i: NORCHIP, 2012. - : IEEE. - 9781467322218 ; , s. 6403128-
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Konferensbidrag (refereegranskat)abstract
- To make systems infinitely scalable is the holy grail of chip design and crux that needs to be solved in order to invent a sustainable design methodology. Network-on-Chip (NoC) has been suggested as this solution as it replaces the traditional buses for on-chip interconnection purposes. However, to reach infinite scalability, off-chip extensions to the NoC protocols are needed in order to maintain scalability at an affordable cost of manufacturability. Going off-chip introduces more levels of complexity when it comes to testing, not only should the chip testing be speedy, the off-chip connections must also be testable in a fast manner, the fastest way being a set of BISTs testing the whole structure in parallel. In this paper, we present a BIST approach for testing an off-chip NoC protocol used in a 4x4 Network-on-Chip configuration. It has 16 processor-nodes implemented on four interconnected plesiochronous Altera Stratix-II FPGA boards, each board hosting a Quad-core NoC.
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| 8. |
- Vasile, Massimiliano, et al.
(författare)
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The Suaineadh Project : a Stepping Stone Towards the Deployment of Large Flexible Structures in Space
- 2010
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Ingår i: Proceedings of the 61<sup>st</sup> International Astronautical Congress. - : the International Astronautical Federation. ; , s. IAC-10-C3.4-
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Konferensbidrag (refereegranskat)abstract
- The Suaineadh project aims at testing the controlled deployment and stabilization of space web. The deployment system is based on a simple yet ingenious control of the centrifugal force that will pull each of the four daughters sections apart. The four daughters are attached onto the four corners of a square web, and will be released from their initial stowed configuration attached to a central hub. Enclosed in the central hub is a specifically designed spinning reaction wheel that controls the rotational speed with a closed loop control fed by measurements from an onboard inertial measurement sensor. Five other such sensors located within the web and central hub provide information on the surface curvature of the web, and progression of the deployment. Suaineadh is currently at an advanced stage of development: all the components are manufactured with the subsystems integrated and are presently awaiting full integration and testing. This paper will present the current status of the Suaineadh project and the results of the most recent set of tests. In particular, the paper will cover the overall mechanical design of the system, the electrical and sensor assemblies, the communication and power systems and the spinning wheel with its control system.
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| 9. |
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| 10. |
- Öberg, Johnny, et al.
(författare)
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A NoC system generator for the Sea-of-Cores era
- 2011
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Ingår i: 8th FPGAworld Conference - Academic Proceedings 2011. - New York, NY, USA : ACM. - 9781450310215 ; , s. 35-40
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Konferensbidrag (refereegranskat)abstract
- Multi-core systems are getting bigger. The number of cores is doubling every 18 months, in corollary with the reformulated Moore's law. Soon, the number of cores that can be integrated together in a system will be so large, that it is appropriate to talk about a new SoC design paradigm, the Sea-of-Cores era. This development will not end, even when CMOS cannot be made any smaller. Instead, with the development of Through-Silicon Vias (TSVs), chips will be stacked in 3D, promising continuous scaling for a very long time ahead. As systems grow, programming and debugging of them will become harder. Methods for generating the systems from higher-level specifications will be necessary to manage design complexity. Also, there will be so many processors to be programmed, that the SW also will have to be automatically generated and distributed, much in the same way as a synthesis and place & route tool is doing today for HW. In this paper, we present a NoC generator that can generate an arbitrarily large Multi-core platform from an XML configuration file, targeted for single-chip FPGA platforms. The NoC generator also generates a device driver prototype together with a small test program that can be used as a template for creating larger programs.
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