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| 56. |
- Farahini, Nasim, et al.
(författare)
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39.9 GOPs/watt multi-mode CGRA accelerator for a multi-standard basestation
- 2013
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Ingår i: 2013 IEEE International Symposium on Circuits and Systems (ISCAS). - : IEEE. - 9781467357609 ; , s. 1448-1451
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Konferensbidrag (refereegranskat)abstract
- This paper presents an industrial case study of using a Coarse Grain Reconfigurable Architecture (CGRA) for a multi-mode accelerator for two kernels: FFT for the LTE standard and the Correlation Pool for the UMTS standard to be executed in a mutually exclusive manner. The CGRA multi-mode accelerator achieved computational efficiency of 39.94 GOPS/watt (OP is multiply-add) and silicon efficiency of 56.20 GOPS/mm2. By analyzing the code and inferring the unused features of the fully programmable solution, an in-house developed tool was used to automatically customize the design to run just the two kernels and the two efficiency metrics improved to 49.05 GOPS/watt and 107.57 GOPS/mm2. Corresponding numbers for the ASIC implementation are 63.84 GOPS/watt and 90.91 GOPS/mm2. Though the ASIC’s silicon and computational efficiency numbers are slightly better, the engineering efficiency of the pre-verified/characterized CGRA solution is at least 10X better than the ASIC solution.
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| 57. |
- Farahini, Nasim, et al.
(författare)
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A conceptual custom super-computer design for real-time simulation of human brain
- 2013
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Ingår i: 2013 21st Iranian Conference on Electrical Engineering, ICEE 2013. - 9781467356343 ; , s. 1-6
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Konferensbidrag (refereegranskat)abstract
- In this paper, we introduce BRIC, a novel custom multi-chip digital computer architecture for simulating in realtime a model of human brain in form of a spiking Bayesian Confidence Propagation Neural Network (BCPNN). The design is conceptually dimensioned for available technology in 2015-2020 with the estimated size of a pizza box, consuming less than 3 kWs of power, delivering 800 Teraflops/sec (single precision multiply operation) and 30 TBs of memory. To the best of our knowledge, this will be the smallest and lowest power real-time brain simulation engine if manufactured. The silicon and computational efficiencies come from use of 3D memory stacking, innovation in algorithm and architectural customization. The chip will be programmable allowing experimentation with variants of the BCPNN brain model.
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| 58. |
- Farahini, Nasim, et al.
(författare)
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A scalable custom simulation machine for the Bayesian Confidence Propagation Neural Network model of the brain
- 2014
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Ingår i: 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC). - : IEEE. - 9781479928163 ; , s. 578-585
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Konferensbidrag (refereegranskat)abstract
- A multi-chip custom digital super-computer called eBrain for simulating Bayesian Confidence Propagation Neural Network (BCPNN) model of the human brain has been proposed. It uses Hybrid Memory Cube (HMC), the 3D stacked DRAM memories for storing synaptic weights that are integrated with a custom designed logic chip that implements the BCPNN model. In 22nm node, eBrain executes BCPNN in real time with 740 TFlops/s while accessing 30 TBs synaptic weights with a bandwidth of 112 TBs/s while consuming less than 6 kWs power for the typical case. This efficiency is three orders better than general purpose supercomputers in the same technology node.
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- Farahini, Nasim, et al.
(författare)
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Atomic stream computation unit based on micro-thread level parallelism
- 2015
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Ingår i: IEEE 26th Application-specific Systems, Architectures and Processors (ASAP) 2015. - : IEEE. - 9781479919246 ; , s. 25-29
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Konferensbidrag (refereegranskat)abstract
- The increasing demand for higher resolution of images and communication bandwidth requires the streaming applications to deal with ever increasing size of datasets. Further, with technology scaling the cost of moving data is reducing at a slower pace compared to the cost of computing. These trends have motivated the proposed micro-architectural reorganization of stream processors by dividing the stream computation into functional computation, address constraints computation and address generation and deploying independent, distributed micro-threads to implement them. This scheme is an alternative to parallelizing them at instruction level. The proposed scheme has two benefits: a more efficient sequencer logic and energy savings in address generation and transportation. These benefits are quantified for a set of streaming applications and show average percentage improvement of 39 in silicon efficiency of the sequencer logic and 23 in total computational efficiency.
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