| 21. |
- Jantsch, Axel, et al.
(author)
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Models of computation and languages for embedded system design
- 2005
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In: IEE Proceedings - Computers and digital Techniques. - : Institution of Engineering and Technology (IET). - 1350-2387 .- 1359-7027. ; 152:2, s. 114-129
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Journal article (peer-reviewed)abstract
- Models of computation (MoC) are reviewed and organised with respect to the time abstraction they use. Continuous time, discrete time, synchronous and untimed MoCs are distinguished. System level models serve a variety of objectives with partially contradicting requirements. Consequently, it is argued that different MoCs are necessary for the various tasks and phases in the design of an embedded system. Moreover, different MoCs have to be integrated to provide a coherent system modelling and analysis environment. The relation between some popular languages and the reviewed MoCs is discussed to find that a given MoC is offered by many languages and a single language can support multiple MoCs. It is contended that it is of importance for the quality of tools and overall design productivity, which abstraction levels and which primitive operators are provided in a language. However, it is observed that there are various flexible ways to do this, e.g. by way of heterogeneous frameworks, coordination languages and embedding of different MoCs in the same language.
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| 22. |
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| 23. |
- Jantsch, Axel
(author)
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Models of Computation for Networks on Chip
- 2006
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In: Proceedings - International Conference on Application of Concurrency to System Design, ACSD 2006.
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Conference paper (peer-reviewed)abstract
- Networks on chip platforms offer the opportunity to introduce a new abstraction level that defines a set of platform services with performance and power characteristics. By making the implementation of these services entirely irrelevant for system design, an effective separation of system design from component design can be achieved. We discuss the principles to formulate network-on-chip services to establish an abstract computational model that exposes all relevant properties of the platform's functionality, performance and power consumption while hiding all irrelevant implementation details. As in many other successful abstractions, these principles are based on separating functionality from time and power aspects to allow for reasoning about these properties at the system level. As a concrete example we formulate a MoC for the Nostrum NoC. It is based on guaranteed bandwidth (GB) and best effort (BE) traffic. The MoC characterizes both GB and BE traffic in terms of closed formulas and allows for efficient composition of traffic.
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| 24. |
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| 25. |
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| 26. |
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| 27. |
- Jantsch, Axel, et al.
(author)
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Power analysis of link level and end-to-end data protection in networks on chip
- 2005
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In: Proceedings - IEEE International Symposium on Circuits and Systems. ; , s. 1770-1773
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Conference paper (peer-reviewed)abstract
- We provide a power analysis for the communication in the Nostrum NoC concluding that power consumption is dominated by the links between switches while the switches and network interfaces contribute with a mere few percent to the power consumption. Further we analyze link level low power encoding techniques with the conclusion, that they spend several times more power than no encoding at all, if normalized for the same performance, which is done by adjusting supply voltage and frequency. Data protection schemes also have the potential to reduce power if voltage levels can be reduced and certain faults can be tolerated. We experiment with link level and end-to-end data protection schemes. They only moderately increase power consumption and have indeed the potential to save power. However, this potential strongly depends on the application traffic patterns and fault models of future technology generations.
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| 28. |
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| 29. |
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| 30. |
- Khatib, Iyad Al, et al.
(author)
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A multiprocessor system-on-chip for real-time biomedical monitoring and analysis : ECG prototype architectural design space exploration
- 2008
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In: ACM Transactions on Design Automation of Electronic Systems. - : Association for Computing Machinery (ACM). - 1084-4309 .- 1557-7309. ; 13:2, s. 31-
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Journal article (peer-reviewed)abstract
- In this article we focus on multiprocessor system-on-chip (MPSoC) architectures for human heart electrocardiogram (ECG) real time analysis as a hardware/software (HW/SW) platform offering an advance relative to state-of-the-art solutions. This is a relevant biomedical application with good potential market, since heart diseases are responsible for the largest number of yearly deaths. Hence, it is a good target for an application-specific system-on-chip (SoC) and HW/SW codesign. We investigate a symmetric multiprocessor architecture based on STMicroelectronics VLIW DSPs that process in real time 12-lead ECG signals. This architecture improves upon state-of-the-art SoC designs for ECG analysis in its ability to analyze the full 12 leads in real time, even with high sampling frequencies, and its ability to detect heart malfunction for the whole ECG signal interval. We explore the design space by considering a number of hardware and software architectural options. Comparing our design with present-day solutions from an SoC and application point-of-view shows that our platform can be used in real time and without failures.
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