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Sökning: WFRF:(Öberg Johnny)

  • Resultat 101-110 av 131
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101.
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102.
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103.
  • Öberg, Johnny, et al. (författare)
  • A NoC system generator for the Sea-of-Cores era
  • 2011
  • Ingår i: 8th FPGAworld Conference - Academic Proceedings 2011. - New York, NY, USA : ACM. - 9781450310215 ; , s. 35-40
  • Konferensbidrag (refereegranskat)abstract
    • Multi-core systems are getting bigger. The number of cores is doubling every 18 months, in corollary with the reformulated Moore's law. Soon, the number of cores that can be integrated together in a system will be so large, that it is appropriate to talk about a new SoC design paradigm, the Sea-of-Cores era. This development will not end, even when CMOS cannot be made any smaller. Instead, with the development of Through-Silicon Vias (TSVs), chips will be stacked in 3D, promising continuous scaling for a very long time ahead. As systems grow, programming and debugging of them will become harder. Methods for generating the systems from higher-level specifications will be necessary to manage design complexity. Also, there will be so many processors to be programmed, that the SW also will have to be automatically generated and distributed, much in the same way as a synthesis and place & route tool is doing today for HW. In this paper, we present a NoC generator that can generate an arbitrarily large Multi-core platform from an XML configuration file, targeted for single-chip FPGA platforms. The NoC generator also generates a device driver prototype together with a small test program that can be used as a template for creating larger programs.
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104.
  • Öberg, Johnny, et al. (författare)
  • A rule-based approach for improving allocation of filter structures in HLS
  • 1996
  • Ingår i: Ninth International Conference on VLSI Design, 1996. Proceedings. - : IEEE conference proceedings. - 0818672285 ; , s. 133-139
  • Konferensbidrag (refereegranskat)abstract
    • A rule based allocator for improving synthesis of filter systems is presented. The principles of the Enhanced AIlocation Rule Language Interpreter (EARLI) are presented. Possible transformations, optimisations and how to express them in EARLI are discussed. Experiments show that relative area gains ranging from 5 to 44%, depending on the chosen target technology, can be achieved using the designers knowledge about the design class. Experiments also indicate that employing direct mapping of CDFG subgraphs onto preoptimised RTL-level macroblocks would have resulted in a relative area gain of 500%. The macroblock had only 16% of the area produced by the HLS-tool
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105.
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107.
  • Öberg, Johnny, et al. (författare)
  • Automatic synthesis of asynchronous circuits from synchronous RTL descriptions
  • 2005
  • Ingår i: Norchip 2005, Proceedings. - : IEEE. - 1424400643 ; , s. 200-205
  • Konferensbidrag (refereegranskat)abstract
    • As the dimensions of ASICs shrink down to the nanometer regime, the variability of the process parameters will increase. This variability threatens to make it extremely difficult to distribute a synchronous clock. all over the chip. Another option would be to replace critical synchronous parts with asynchronous counterparts with the same functionality. The main problems are, first, there is no established tool-flow that makes it easy for a designer to design an asynchronous circuits, and, second, there are no established design automation tools, except a few experimental ones. In addition, most designers today are trained to design synchronous circuits and have to be retrained. In this paper we present a method that solves all three of these problems, i.e., it allows a designer to start in the synchronous domain, and then automatically transform the synchronous representation of the circuit into an asynchronous one.
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