| 191. |
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| 192. |
- Olsson, Thomas, et al.
(författare)
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A Digitally Controlled Low-Power Clock Multiplier for Globally Asynchronous Locally Synchronous Designs
- 2000
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Ingår i: The 2000 IEEE International Symposium on Circuits and Systems. Proceedings.. - 0780354826 ; 3, s. 13-16
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Konferensbidrag (refereegranskat)abstract
- Partitioning large high-speed globally synchronous ASICs into locally clocked blocks reduces clock skew problems and if handled correctly it also reduces the power consumption. However, to achieve these positive effects, the blocks need on-chip clock generators having properties such as small area and low power consumption. Therefore, a low power, high frequency, small area digitally controlled on-chip clock generator is designed and fabricated using a 0.35 μm process. The clock generator delivers up to 1.15 GHz at 3.3 V supply voltage. At 1 V supply voltage, it delivers up to 92 MHz while consuming 0.16 mW
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| 193. |
- Olsson, Thomas, et al.
(författare)
-
A digitally controlled on-chip clock multiplier for globally asynchronous locally synchronous systems
- 1999
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Ingår i: Circuits and Systems, 1999. 42nd Midwest Symposium on. ; 1, s. 84-87
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Konferensbidrag (refereegranskat)abstract
- For large high-speed globally synchronous ASICs, designing the clock distribution net becomes a troublesome task. Besides problems caused by clock skew, the clock net also is a major source of power consumption. Partitioning the design into locally clocked blocks reduces clock skew problems and if handled correctly it also helps reducing power consumption. However, to achieve these positive effects, the blocks need on-chip clocks having properties as small area and low power consumption. Therefore, a low power small area digitally controlled on-chip clock generator is designed
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| 194. |
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| 195. |
- O'Nils, Mattias, et al.
(författare)
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Design of D-AMPS Channel Decoder with Codesign Methodologies
- 1996
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Ingår i: BEC '96, the 5th Biennial Baltic Electronics Conference, October 7-11, 1996, Tallinn, Estonia : proceedings. - Tallinn, Estonia : Tallinn Technical University. - 9789985590263 ; , s. 491-
-
Konferensbidrag (refereegranskat)abstract
- This paper is a case study on tool based codesign methodology. The presented methods are observed by applying a D-AMPS channel decoder design to a codesign research tool-kit. The channel decoder functionality is described with five thousand lines of C code. The analysis (profiling, estimation, hardware-software partitioning and verification) of the C description are presented in the paper.
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| 196. |
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| 197. |
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| 198. |
- Patan, A. K., et al.
(författare)
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Design and Implementation of Optimized Register File for Streaming Applications
- 2021
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Ingår i: 2021 25th International Symposium on VLSI Design and Test, VDAT 2021. - : Institute of Electrical and Electronics Engineers (IEEE).
-
Konferensbidrag (refereegranskat)abstract
- The increased demand for energy-efficient solutions compels system architects to explore the opportunities for minimizing area and power in the critical parts of a system. The register file is one such essential and critical component of any processor system that provides local storage for computing hardware such as arithmetic and logical unit. In this paper, we present an optimized design and implementation of a synthesizable register file that reduces the area and power consumption over an existing design. The proposed design is functionally equivalent to the existing design and uses latches in its core as main storage elements as opposed to the flip-flops; thus, reducing the area and power consumption. The proposed design has 10% less area and 23% less leakage power than the existing design when synthesized using a CMOS 45nm process libraries. Furthermore, the back-end implementation results show that the proposed design has 13% less core utilization and 2.3X less power.
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| 199. |
- Penolazzi, Sandro, et al.
(författare)
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A General Approach to High-Level Energy and Performance Estimation in SoCs
- 2009
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Ingår i: 22ND INTERNATIONAL CONFERENCE ON VLSI DESIGN HELD JOINTLY WITH 8TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS. - 9780769535067 ; , s. 200-205
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Konferensbidrag (refereegranskat)abstract
- We present a high-level methodology for efficient and accurate estimation of energy and performance in SoCs at Functional Untimed Level. We then validate the proposed method against gate level for accuracy and against TLM-PV for speed. We show that the method is within 15% of gate-level accuracy and in aver-age 28x faster than TLM-PV, for the benchmark applications selected.
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| 200. |
- Penolazzi, Sandro, et al.
(författare)
-
A general approach to high-level energy and performance estimation in system-on-chip architectures
- 2009
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Ingår i: Journal of Low Power Electronics. - : American Scientific Publishers. - 1546-1998. ; 5:3, s. 373-384
-
Tidskriftsartikel (refereegranskat)abstract
- We present a high-level methodology for efficient and accurate estimation of energy and performance in SoCs. Differently from the most common approaches, which rely on Transaction-Level Modeling (TLM), we infer energy and performance figures directly from the Functional Untimed Level, by running the algorithmic specification natively on a common host machine. We then validate the proposed method against gate level for accuracy and against TLM-PV for speed. We show that the method is within 17% of gate-level accuracy and in average 28x faster than TLM-PV, for the benchmark applications selected.
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