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- Bhide, Ameya, et al.
(författare)
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An 8-GS/s 200-MHz Bandwidth 68-mW ΔΣ DAC in 65-nm CMOS
- 2013
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 60:7, s. 387-391
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Tidskriftsartikel (refereegranskat)abstract
- This brief presents an 8-GS/s 12-bit input ΔΣ digital-to-analog converter (DAC) with 200-MHz bandwidth in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1–1 digital ΔΣ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. The two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each channel to operate at half the sampling rate, which is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results show that the DAC achieves 200-MHz bandwidth, 26-dB SNDR, and $-$57-dBc IMD3, with a power consumption of 68 mW at 1-V digital and 1.2-V analog supplies. This architecture shows potential for use in transmitter baseband for wideband wireless communication.
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| 5. |
- Bhide, Ameya, 1980-, et al.
(författare)
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Critical Path Analysis of Two-channel Interleaved Digital MASH ΔΣ Modulators
- 2013
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Ingår i: 2013 NORCHI, 11–12 November, 2013, Vilnius, Lithuania. - : IEEE. - 9781479916474 ; , s. 1-4
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Konferensbidrag (refereegranskat)abstract
- Implementation of wireless wideband transmitters using ΔΣ DACs requires very high speed modulators. Digital MASH ΔΣ modulators are good candidates for speed enhancement using interleaving because they require only adders and can be cascaded. This paper presents an analysis of the integrator critical path of two-channel interleaved ΔΣ modulators. The bottlenecks for a high-speed operation are identified and the performance of different logic styles is compared. Static combinational logic shows the best trade-off and potential for use in such high speed modulators. A prototype 12-bit second order MASH ΔΣ modulator designed in 65 nm CMOS technology based on this study achieves 9 GHz operation at 1 V supply.
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- Duong, Quoc-Tai, et al.
(författare)
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Highly linear open-loop output driver design for high speed capacitive DACs
- 2013
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Ingår i: 2013 NORCHIP, 11–12 November, 2013, Vilnius, LITHUANIA. - 9781479916474 ; , s. 1-4
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Konferensbidrag (refereegranskat)abstract
- Design of a high speed output driver for capacitive digital-to-analog converters (SC DACs) is presented. As the output voltage swing of those DACs is usually greater than 300 mVpp the driver is designed for large signal operation that is a challenge in terms of the DAC linearity. Two non-linearity cancellation techniques are applied to the driver circuit, the derivative superposition (DS) and the resistive source degeneration resulting in HD3 <; -70 dB and HD2 <; -90 dB over the band of 0.5-4 GHz in 65-nm CMOS. For the output swing of 300 mVpp and 1.2 V supply its power consumption is 40 mW. For verification the driver is implemented in a 12-bit pipeline SC DAC. In simulations the complete Nyquist-rate DAC achieves SFDR of 64 dB for signal bandwidth up to 2.2 GHz showing a negligible non-linearity contribution by the designed driver for signal frequencies up to 1.3 GHz and a degradation by 3 dB at 2.2 GHz.
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- Fazli Yeknami, Ali, et al.
(författare)
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A 0.5-V 250-nW 65-dB SNDR Passive ΔΣ Modulator for Medical Implant Devices
- 2013
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Ingår i: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 May, 2013. - 9781467357609 ; , s. 2010-2013
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Konferensbidrag (refereegranskat)abstract
- A 0.5-V ultra-low-power second-order DT DS modulator is presented in this paper for medical implant devices. The modulator employs 2nd-order passive low-pass filter and ultra-low-voltage building blocks, including preamplifier, regenerative comparator, and clock controller, in order to enable operation near 0.5 V supply. A low-noise and gain-enhanced single-stage preamplifier is developed using a body-driven technique. Passive filter is gain boosted by power-efficient charge-redistribution amplification scheme. Designed in a 65nm CMOS technology, the modulator achieves 65 dB peak SNDR over a 500 Hz signal bandwidth, while it consumes 250 nW from a 0.5 V supply. The modulator is functional at 0.45V and obtains 52 dB SNR, while consuming 200 nW.
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- Fazli Yeknami, Ali, et al.
(författare)
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A 0.7-V 400-nW Fourth-Order Active-Passive Delta-Sigma Modulator with One Active Stage
- 2013
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Konferensbidrag (refereegranskat)abstract
- A 0.7 V 400 nW fourth-order active-passive ΔΣ modulator with one active stage is presented in this paper using standard CMOS 65 nm technology. The modulator achieves 84 dB SNR and 80.3 dB SNDR in a signal bandwidth of 500 Hz with a sampling frequency of 256 kHz. The input-feedforward architecture is used to improve the voltage swing before the comparator of the traditional passive modulators, which enables simpler comparator design with no preamplifier as well as cascading three successive power-efficient passive filters. The first active stage is used to reduce the comparator's noise and offset and to minimize the capacitive area. The modulator achieves a high power-efficiency (47 fJ/step) in terms of widely used figure of merit.
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- Fazli Yeknami, Ali, et al.
(författare)
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A 0.7-V 600-nW 87-dB SNDR DT-Delta Sigma Modulator with Partly Body-Driven and Switched Op-amps for Biopotential Signal Acquisition
- 2012
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Ingår i: 2012 IEEE BIOMEDICAL CIRCUITS AND SYSTEMS CONFERENCE (BIOCAS): INTELLIGENT BIOMEDICAL ELECTRONICS AND SYSTEM FOR BETTER LIFE AND BETTER ENVIRONMENT. - : IEEE. - 9781467322911 ; , s. 336-339
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Konferensbidrag (refereegranskat)abstract
- A 0.7 V third-order DT Delta Sigma modulator is presented in this paper for measurement of biopotential signals in portable medical applications. Switched-opamp technique has been adopted in this design to eliminate the critical switches, which leads to low-voltage and low-power consumption. The modulator employs new partially body-driven gain-enhanced amplifiers for low-voltage operation in order to compensate the dc gain degradation. Switched-opamp approach is embedded in amplifiers and CMFB circuits to reduce the power consumption. The major building blocks, such as the proposed Class AB gain-enhanced amplifiers and the low-voltage comparator, use body-biased p-MOS to reduce the threshold voltage, thus providing more voltage headroom in the low voltage environment. Noise analysis, as a critical step in the design of a high resolution ADC, is also provided. Designed in a 65nm CMOS technology, the modulator achieves 87 dB peak SNDR over a 500 Hz signal bandwidth, while it consumes 600-nW from a 0.7 V supply.
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- Fazli Yeknami, Ali, et al.
(författare)
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A 2.1 mu W 80 dB SNR DT Delta I pound modulator for medical implant devices in 65 nm CMOS
- 2013
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Ingår i: Analog Integrated Circuits and Signal Processing. - : Springer. - 0925-1030 .- 1573-1979. ; 77:1, s. 69-78
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a simple and robust low-power Delta I pound modulator for accurate ADCs in implantable cardiac rhythm management devices such as pacemakers. Taking advantage of the very low signal bandwidth of 500 Hz which enables high oversampling ratio, the objective is to obtain high SNDR and low power consumption, while limiting the complexity of the modulator to a second-order architecture. Significant power reduction is achieved by utilizing a two-stage load-compensated OTA as well as the low-V-T devices in analog circuits and switches, allowing the modulator to operate at 0.9 V supply. Fabricated in a 65 nm CMOS technology, the modulator achieves 80 dB peak SNR and 76 dB peak SNDR over a 500 Hz signal bandwidth. With a power consumption of 2.1 mu W, the modulator obtains 0.4 pJ/step FOM. To the authors knowledge, this is the lowest reported FOM, compared to the previously reported second-order modulators for such low-speed applications. The achieved FOM is also comparable to the best reported results from the higher-order Delta I pound modulators.
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