| 1. |
- Aghaee Ghaleshahi, Nima, et al.
(författare)
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Adaptive Temperature-Aware SoC Test Scheduling Considering Process Variation
- 2011
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Ingår i: <em>Digital System Design (DSD), 2011 14th Euromicro Conference on</em>. - : IEEE. - 9781457710483 ; , s. 197-204
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Konferensbidrag (refereegranskat)abstract
- High temperature and process variation areundesirable effects for modern systems-on-chip. The hightemperature is a prominent issue during test and should be takencare of during the test process. Modern SoCs, affected by largeprocess variation, experience rapid and large temperaturedeviations and, therefore, a traditional static test schedule which isunaware of these deviations will be suboptimal in terms of speedand/or thermal-safety. This paper presents an adaptive testscheduling method which addresses the temperature deviationsand acts accordingly in order to improve the test speed andthermal-safety. The proposed method is divided into acomputationally intense offline-phase, and a very simple online-phase.In the offline-phase a schedule tree is constructed, and inthe online-phase the appropriate path in the schedule tree istraversed, step by step and based on temperature sensor readings.Experiments have demonstrated the efficiency of the proposedmethod.
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| 2. |
- Aghaee Ghaleshahi, Nima, et al.
(författare)
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Heuristics for Adaptive Temperature-Aware SoC Test Scheduling Considering Process Variation
- 2011
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Ingår i: <em>The 11th Swedish System-on-Chip Conference, Varberg, Sweden, May 2-3, 2011</em>.
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- High working temperature and process variation are undesirable effects for modern systems-on-chip. The high temperature should be taken care of during the test. On the other hand, large process variations induce rapid and large temperature deviations causing the traditional static test schedules to be suboptimal in terms of speed and/or thermal-safety. A remedy to this problem is an adaptive test schedule which addresses the temperature deviations by reacting to them. Our adaptive method is divided into a computationally intense offline-phase, and a very simple online-phase. In this paper, heuristics are proposed for the offline phase in which the optimized schedule tree is found. In the online-phase, based on the temperature sensor readings the appropriate path in the schedule tree is traversed. Experiments are made to tune the proposed heuristics and to demonstrate their efficiency.
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| 3. |
- Aghaee Ghaleshahi, Nima, et al.
(författare)
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Process-variation and Temperature Aware SoC Test Scheduling Technique
- 2013
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Ingår i: Journal of electronic testing. - : Springer. - 0923-8174 .- 1573-0727. ; 29:4, s. 499-520
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Tidskriftsartikel (refereegranskat)abstract
- High temperature and process variation are undesirable phenomena affecting modern Systems-on-Chip (SoC). High temperature is a well-known issue, in particular during test, and should be taken care of in the test process. Modern SoCs are affected by large process variation and therefore experience large and time-variant temperature deviations. A traditional test schedule which ignores these deviations will be suboptimal in terms of speed or thermal-safety. This paper presents an adaptive test scheduling method which acts in response to the temperature deviations in order to improve the test speed and thermal safety. The method consists of an offline phase and an online phase. In the offline phase a schedule tree is constructed and in the online phase the appropriate path in the schedule tree is traversed based on temperature sensor readings. The proposed technique is designed to keep the online phase very simple by shifting the complexity into the offline phase. In order to efficiently produce high-quality schedules, an optimization heuristic which utilizes a dedicated thermal simulation is developed. Experiments are performed on a number of SoCs including the ITC'02 benchmarks and the experimental results demonstrate that the proposed technique significantly improves the cost of the test in comparison with the best existing test scheduling method.
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| 4. |
- Aghaee Ghaleshahi, Nima, et al.
(författare)
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Process-Variation and Temperature Aware SoC Test Scheduling Using Particle Swarm Optimization
- 2011
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Ingår i: <em>The 6th IEEE International Design and Test Workshop (IDT'11), Beirut, Lebanon, December 11–14, 2011.</em>. - : IEEE. - 9781467304689 - 9781467304672
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Konferensbidrag (refereegranskat)abstract
- High working temperature and process variation are undesirable effects for modern systems-on-chip. It is well recognized that the high temperature should be taken care of during the test process. Since large process variations induce rapid and large temperature deviations, traditional static test schedules are suboptimal in terms of speed and/or thermalsafety. A solution to this problem is to use an adaptive test schedule which addresses the temperature deviations by reacting to them. We propose an adaptive method that consists of a computationally intense offline-phase and a very simple onlinephase. In the offline-phase, a near optimal schedule tree is constructed and in the online-phase, based on the temperature sensor readings, an appropriate path in the schedule tree is traversed. In this paper, particle swarm optimization is introduced into the offline-phase and the implications are studied. Experimental results demonstrate the advantage of the proposed method.
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| 5. |
- Aghaee Ghaleshahi, Nima, et al.
(författare)
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Temperature-Aware SoC Test Scheduling Considering Inter-Chip Process Variation
- 2010
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Ingår i: <em>19th IEEE Asian Test Symposium (ATS10), Shanghai, China, December 1-4, 2010.</em>. - 9781424488414
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Konferensbidrag (refereegranskat)abstract
- Systems on Chip implemented with deep submicron technologies suffer from two undesirable effects, high power density, thus high temperature, and high process variation, which must be addressed in the test process. This paper presents two temperature-aware scheduling approaches to maximize the test throughput in the presence of inter-chip process variation. The first approach, an off-line technique, improves the test throughput by extending the traditional scheduling method. The second approach, a hybrid one, improves further the test throughput with a chip classification scheme at test time based on the reading of a temperature sensor. Experimental results have demonstrated the efficiency of the proposed methods.
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| 6. |
- Aghaee Ghaleshahi, Nima, et al.
(författare)
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Temperature-Gradient Based Burn-In for 3D Stacked ICs
- 2013
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Ingår i: <em>The 12th Swedish System-on-Chip Conference (SSoCC 2013), Ystad, Sweden, May 6-7, 2013 (not reviewed, not printed).</em>.
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- 3D Stacked IC fabrication, using Through-Silicon-Vias, is a promising technology for future integrated circuits. However, large temperature gradients may exacerbate early-life-failures to the extent that the commercialization of 3D Stacked ICs is challenged. The effective detection of these early-life-failures requires that burn-in is performed when the IC’s temperatures comply with the thermal maps that properly specify the temperature gradients. In this paper, two methods that efficiently generate and maintain the specified thermal maps are proposed. The thermal maps are achieved by applying heating and cooling intervals to the chips under test through test access mechanisms. Therefore, no external heating system is required. The scheduling of the heating and cooling intervals is based on thermal simulations. The schedule generation is guided by functions that are derived from the temperature equations. Experimental results demonstrate the efficiency of the proposed method.
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| 7. |
- Aghaee Ghaleshahi, Nima, et al.
(författare)
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Temperature-Gradient Based Test Scheduling for 3D Stacked ICs
- 2013
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Ingår i: 2013 IEEE International Conference on Electronics, Circuits, and Systems. - : IEEE conference proceedings. - 9781479924523 ; , s. 405-408
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Konferensbidrag (refereegranskat)abstract
- Defects that are dependent on temperature-gradients (e.g., delay-faults) introduce a challenge for achieving an effective test process, in particular for 3D ICs. Testing for such defects must be performed when the proper temperature gradients are enforced on the IC, otherwise these defects may escape the test. In this paper, a technique that efficiently heats up the IC during test so that it complies with the specified temperature gradients is proposed. The specified temperature gradients are achieved by applying heating sequences to the cores of the IC under test trough test access mechanism; thus no external heating mechanism is required. The scheduling of the test and heating sequences is based on thermal simulations. The schedule generation is guided by functions derived from the IC's temperature equation. Experimental results demonstrate that the proposed technique offers considerable test time savings.
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| 8. |
- Aminifar, Amir, et al.
(författare)
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Control-Quality Driven Design of Cyber-Physical Systems with Robustness Guarantees
- 2013
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Ingår i: Design, Automation & Test in Europe (DATE 2013). - : IEEE. - 1530-1591. - 9781467350716 ; , s. 1093-1098
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Konferensbidrag (refereegranskat)abstract
- Many cyber-physical systems comprise several control applications sharing communication and computation resources. The design of such systems requires special attention due to the complex timing behavior that can lead to poor control quality or even instability. The two main requirements of control applications are: (1) robustness and, in particular, stability and (2) high control quality. Although it is essential to guarantee stability and provide a certain degree of robustness even in the worst-case scenario, a design procedure which merely takes the worst-case scenario into consideration can lead to a poor expected (average-case) control quality, since the design is solely tuned to a scenario that occurs very rarely. On the other hand, considering only the expected quality of control does not necessarily provide robustness and stability in the worst-case. Therefore, both the robustness and the expected control quality should be taken into account in the design process. This paper presents an efficient and integrated approach for designing high-quality cyber-physical systems with robustness guarantees.
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| 9. |
- Aminifar, Amir, et al.
(författare)
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Control-Quality Driven Task Mapping for Distributed Embedded Control Systems
- 2011
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Ingår i: <em>Embedded and Real-Time Computing Systems and Applications (RTCSA), 2011 IEEE 17th International Conference on</em>. - : IEEE. - 9781457711183 ; , s. 133-142
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Konferensbidrag (refereegranskat)abstract
- Many embedded control systems are implemented on execution platforms with several computation nodes and communication components. Distributed embedded control systems typically comprise multiple control loops that share the available computation and communication resources of the platform. It is well known that such resource sharing leads to complex delay characteristics that degrade the control quality if not properly taken into account at design time. Scheduling in computation nodes and communication infrastructure, as well as execution periods of the controllers impact the delay characteristics and, consequently, the control quality. In addition, mapping of tasks on computation nodes affect both scheduling of tasks and messages, and the assignment of periods of the control applications. Therefore, control synthesis must be considered during mapping, scheduling, and period assignment in order to achieve high control quality. This paper presents a control-quality optimization approach for integrated mapping, scheduling, period selection, and control synthesis for distributed embedded control systems.
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| 10. |
- Aminifar, Amir, et al.
(författare)
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Designing Bandwidth-Efficient Stabilizing Control Servers
- 2013
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Ingår i: IEEE Real-Time Systems Symposium, RTSS 2013. - : IEEE. - 9781479920075 ; , s. 298-307, s. 298-307
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Konferensbidrag (refereegranskat)abstract
- Guaranteeing stability of control applications in embedded systems, or cyber-physical systems, is perhaps the alpha and omega of implementing such applications. However, as opposed to the classical real-time systems where often the acceptance criterion is meeting the deadline, control applications do not primarily enforce hard deadlines. In the case of control applications, stability is considered to be the main design criterion and can be expressed in terms of the amount of delay and jitter a control application can tolerate before instability. Therefore, new design and analysis techniques are required for embedded control systems. In this paper, the analysis and design of such systems considering server-based resource reservation mechanism are addressed. The benefits of employing servers are manifold: (1) providing a compositional framework, (2) protection against other tasks misbehaviors, and (3) systematic bandwidth assignment. We propose a methodology for designing bandwidth-efficient servers to stabilize control tasks.
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