| 1. |
- Abdalla, Suliman, et al.
(författare)
-
Architecture and Circuit Design for Color X-Ray Pixal Array Detector Read-Out Electronics
- 2007
-
Ingår i: 24th Norchip Conference, 2006. - New York : IEEE conference proceedings. - 9781424407729 ; , s. 271-276
-
Konferensbidrag (refereegranskat)abstract
- This paper proposes an area- and power-efficient implementation of the read-out electronics for color X-ray pixel detectors for imaging. Introducing multiple levels of energy discrimination will increase the complexity of the read-out electronics in each pixel. The proposed architecture has full resolution for the intensity and reduced resolution for the energy spectrum (color), which leads to a good compromise of image quality and circuit complexity. We show that the increase in complexity, compared to single energy-range pixel, will lead to increase in circuit area of less than 20%.
|
|
| 2. |
|
|
| 3. |
- Cao, Cao, et al.
(författare)
-
Synthesis tool for low-power finite-state machines with mixed synchronous/asynchronous state memory
- 2006
-
Ingår i: IEE Proceedings - Computers and digital Techniques. - : Institution of Engineering and Technology (IET). - 1350-2387 .- 1359-7027. ; 153:4, s. 243-248
-
Tidskriftsartikel (refereegranskat)abstract
- An efficient way to obtain finite-state machines (FSMs) with low-power consumption is to partition the machine into two or more sub-FSMs and then use dynamic power management where all sub-FSMs not active are shut down, with the effect of reducing dynamic power dissipation. Thus, FSM partitioning algorithms and register-transfer-level power estimation functions are the main focus of the paper as these are key issues in the design of a computer-aided design tool for synthesis of low-power partitioned FSMs. An implementation architecture is targeted, which is based on both synchronous and asynchronous state memory elements that enable larger power reductions than fully synchronous architectures do. Power reductions of up to 77 have been achieved at a cost of an 18 increase in area.
|
|
| 4. |
- Lawal, Najeem, et al.
(författare)
-
Address Generation for FPGA RAMs for Efficient Implementation of Real-Time Video Processing Systems
- 2005
-
Ingår i: Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL. - : IEEE conference proceedings. - 0780393627 ; , s. 136-141
-
Konferensbidrag (refereegranskat)abstract
- FPGA offers the potential of being a reliable, and high-performance reconfigurable platform for the implementation of real-time video processing systems. To utilize the full processing power of FPGA for video processing applications, optimization of memory accesses and the implementation of memory architecture are important issues. This paper presents two approaches, base pointer approach and distributed pointer approach, to implement accesses to on-chip FPGA Block RAMs. A comparison of the experimental results obtained using the two approaches on realistic image processing systems design cases is presented. The results show that compared to the base pointer approach the distributed pointer approach increases the potential processing power of FPGA, as a reconfigurable platform for video processing systems.
|
|
| 5. |
- Lawal, Najeem, et al.
(författare)
-
C++ based System Synthesis of Real-Time Video Processing Systems targeting FPGA Implementation
- 2006
-
Ingår i: Proceedings of the FPGA World Conference 2006.
-
Konferensbidrag (refereegranskat)abstract
- Implementing real-time video processing systems put high requirements on computation and memory performance. FPGAs have shown to be an effective implementation architecture for these systems. However, the hardware based design flow for FPGAs make the implementation task complex. The system synthesis tool presented in this paper reduces this design complexity. The synthesis is done from a SystemC based coarse grain data flow graph that captures the video processing system. The data flow graph is optimized and mapped onto an FPGA. The results from real-life video processing systems clearly show that the presented tool produces effective implementations.
|
|
| 6. |
- Lawal, Najeem, et al.
(författare)
-
Embedded FPGA memory requirements for real-time video processing applications
- 2005
-
Ingår i: 23rd NORCHIP Conference 2005. - : IEEE conference proceedings. - 1424400643 ; , s. 206-209
-
Konferensbidrag (refereegranskat)abstract
- FPGAs show interesting properties for real-time implementation of video processing systems. An important feature is the available on-chip RAM blocks embedded on the FPGAs. This paper presents an analysis of the current and future requirements of video processing systems put on these embedded memory resources. The analysis is performed such that a set of video processing systems are allocated onto different existing and extrapolated FPGA architectures. The analysis shows that FPGAs should support multiple memory sizes to take full advantage of the architecture. These results are valuable for both designers of systems and for planning the development of new FPGA architectures
|
|
| 7. |
- Lawal, Najeem, 1974-
(författare)
-
Memory Synthesis for FPGA Implementation of Real-Time Video Processing Systems
- 2009
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- In this thesis, both a method and a tool to enable efficient memory synthesis for real-time video processing systems on field programmable logic array are presented. In real-time video processing system (RTVPS), a set of operations are repetitively performed on every image frame in a video stream. These operations are usually computationally intensive and, depending on the video resolution, can also be very data transfer dominated. These operations, which often require data from several consecutive frames and many rows of data within each frame, must be performed accurately and under real-time constraints as the results greatly affect the accuracy of application. Application domains of these systems include machine vision, object recognition and tracking, visual enhancement and surveillance. Developments in field programmable gate arrays (FPGAs) have been the motivation for choosing them as the platform for implementing RTVPS. Essential logic resources required in RTVPS operations are currently available and are optimized and embedded in modern FPGAs. One such resource is the embedded memory used for data buffering during real-time video processing. Each data buffer corresponds to a row of pixels in a video frame, which is allocated using a synthesis tool that performs the mapping of buffers to embedded memories. This approach has been investigated and proven to be inefficient. An efficient alternative employing resource sharing and allocation width pipelining will be discussed in this thesis. A method for the optimised use of these embedded memories and, additionally, a tool supporting automatic generation of hardware descriptions language (HDL) modules for the synthesis of the memories according to the developed method are the main focus of this thesis. This method consists of the memory architecture, allocation and addressing. The central objective of this method is the optimised use of embedded memories in the process of buffering data on-chip for an RVTPS operation. The developed software tool is an environment for generating HDL codes implementing the memory sub-components. The tool integrates with the Interface and Memory Modelling (IMEM) tools in such a way that the IMEM’s output - the memory requirements of a RTVPS - is imported and processed in order to generate the HDL codes. IMEM is based on the philosophy that the memory requirements of an RTVPS can be modelled and synthesized separately from the development of the core RTVPS algorithm thus freeing the designer to focus on the development of the algorithm while relying on IMEM for the implementation of memory sub-components.
|
|
| 8. |
- Lawal, Najeem, 1974-
(författare)
-
Memory Synthesis for FPGA Implementation of Real-Time Video Processing Systems
- 2006
-
Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- In this thesis, both a method and a tool to enable efficient memory synthesis for real-time video processing systems on field programmable logic array are presented. In real-time video processing system (RTVPS), a set of operations are repetitively performed on every image frame in a video stream. These operations are usually computationally intensive and, depending on the video resolution, can also be very data transfer dominated. These operations, which often require data from several consecutive frames and many rows of data within each frame, must be performed accurately and under real-time constraints as the results greatly affect the accuracy of application. Application domains of these systems include object recognition, object tracking and surveillance. Developments in field programmable gate array (FPGA) have been the motivation for choosing them as the platform for implementing RTVPS. Essential logic resources required in RTVPS operation are currently available optimized and embedded in modern FPGAs. One such resource is the embedded memory used for data buffering during real-time video processing. Each data buffer corresponds to a row of pixels in a video frame, which is allocated using a synthesis tool that performs the mapping of buffers to embedded memories. This approach has been investigated and proven to be inefficient. An efficient alternative employing resource sharing and allocation width pipelining will be discussed in this thesis. A method for the optimal use of these embedded memories and, additionally, a tool supporting automatic generation of hardware descriptions language (HDL) codes for the synthesis of the memories according to the developed method are the main focus of this thesis. This method consists of the memory architecture, allocation and addressing. The central objective of this method is the optimal use of embedded memories in the process of buffering data on-chip for an RVTPS operation. The developed software tool is an environment for generating HDL codes implementing the memory sub-components. The tool integrates with the Interface and Memory Modelling (IMEM) tools in such a way that the IMEM’s output - the memory requirements of a RTVPS - is imported and processed in order to generate the HDL codes. IMEM is based on the philosophy that the memory requirements of an RTVPS can be modelled and synthesized separately from the development of the core RTVPS algorithm thus freeing the designer to focus on the development of the algorithm while relying on IMEM for the implementation of memory sub-components.
|
|
| 9. |
- Lawal, Najeem, et al.
(författare)
-
Power-aware automatic constraint generation for FPGA based real-time video processing systems
- 2007
-
Ingår i: 25th Norchip Conference, NORCHIP. - New York : IEEE conference proceedings. - 9781424415168 ; , s. 124-128
-
Konferensbidrag (refereegranskat)abstract
- The introduction of embedded DSP blocks and embedded memory has made FPGAs an attractive architecture for implementation of real-time video processing systems. The big bottle neck of the FPGA compared to other programmable architectures is the complex programming model. This paper presents an automatic generation of placement and routing constraints for FPGA implementation of real-time video processing systems as one step to automate the programming model. The constraint generator targets lower power consumption, better resource utilization and reduced development time. Results show that a 28 % reduction in dynamic power can be achieved using the proposed approach over traditional logic to memory mapping.
|
|
| 10. |
- Lawal, Najeem, et al.
(författare)
-
Ram allocation algorithm for video processing applications on FPGA
- 2006
-
Ingår i: Journal of Circuits, Systems and Computers. - 0218-1266. ; 15:5, s. 679-699
-
Tidskriftsartikel (refereegranskat)abstract
- This paper presents an algorithm for the allocation of on-chip FPGA Block RAMs for the implementation of Real-Time Video Processing Systems. The effectiveness of the algorithm is shown through the implementation of realistic image processing systems. The algorithm, which is based on a heuristic, seeks the most cost-effective way of allocating memory objects to the FPGA Block RAMs. The experimental results obtained, show that this algorithm generates results which are close to the theoretical optimum for most design cases.
|
|
