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41.
  • Chen, Zhipeng, et al. (författare)
  • A Worst Case Performance Model for TDM Virtual Circuit in NoCs
  • 2010
  • Ingår i: NETWORK AND PARALLEL COMPUTING. - Berlin : Springer Berlin/Heidelberg. - 9783642156717 ; , s. 452-461
  • Konferensbidrag (refereegranskat)abstract
    • In Network-on-Chip (NoC), Time-Division-Mutiplexing (TDM) Virtual Circuit (VC) is well recognized as being capable to provide guaranteed services in both latency and bandwidth. We propose a method of modeling TDM based VC by using Network Calculus. We derive a tight upper bound of end-to-end delay and buffer requirement for individual VC. The performance analysis using Latency-Rate server is also presented in comparsion with our Performance model for TDM Virtual Circuit in NoCs (Pemvin). We conducted experiments on comparing Pemvin to the Latency-Rate server model. Our experiment results show the improvement of Pemvin on tightening the upper bound of end-to-end delay and buffer requirement.
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46.
  • Deb, Abhijit Kumar, et al. (författare)
  • System design for DSP applications in transaction level modeling paradigm
  • 2004
  • Ingår i: 41st Design Automation Conference, Proceedings 2004. - New York, NY, USA : ACM. - 1581138288 ; , s. 466-471
  • Konferensbidrag (refereegranskat)abstract
    • In this paper, we systematically define three transaction level models (TLMs), which reside at different levels of abstraction between the functional and the implementation model of a DSP system. We also show a unique language support to build the TLMs. Our results show that the abstract TLMs can be built and simulated much faster than the implementation model at the expense of a reasonable amount of simulation accuracy.
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47.
  • Deb, Abhijit Kumar, et al. (författare)
  • System design for DSP applications using the MASIC methodology
  • 2004
  • Ingår i: DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS. - LOS ALAMITOS : IEEE COMPUTER SOC. - 0769520855 ; , s. 630-635
  • Konferensbidrag (refereegranskat)abstract
    • Expensive top-down iterations are often required in the design cycle of complex DSP systems. In this paper, we introduce two levels of abstraction in the design flow by, systematically categorizing the architectural decisions. As a result, the top-down iteration loop is broken. We also present a technique to capture and inject the architectural decisions such that the system models can be created and simulated efficiently. The concepts are illustrated by a realistic speech processing example, which is implemented using the AMBA on-chip architecture. Our methodology offers a smooth path from the functional modeling phase to the implementation level, facilitates the reuse of HW and SW components, and enjoys existing tool support at the backend.
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48.
  • Deivasigamani, M., et al. (författare)
  • Concept and design of exhaustive-parallel search algorithm for Network-on-Chip
  • 2011
  • Ingår i: Int. Syst. Chip Conf.. - 9781457716164 ; , s. 150-155
  • Konferensbidrag (refereegranskat)abstract
    • This paper presents the concept and design of exhaustive-parallel search algorithm for Network-on-Chip. The proposed parallel algorithm searches minimal path between source and destination in a forward-wave-propagation manner. The algorithm guarantees setup latency if the setup path exists. A high performance switch is designed to support exhaustive-parallel search algorithm. The NoC fabric is designed for 88 mesh architecture and its performance is evaluated.
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50.
  • Ebrahimi, Masoumeh, et al. (författare)
  • Rescuing healthy cores against disabled routers
  • 2014
  • Konferensbidrag (refereegranskat)abstract
    • A router may be temporarily or permanently disabled in NoCs for several reasons such as saving power, occurring faults or testing. Disabling a router, however, may have a severe impact on the performance or functionality of the entire system if it results in disconnecting the core from the network. In this paper, we propose a deadlock-free routing algorithm which allows the core to stay connected to the system and continue its normal operation when its connected router is disabled. Our analysis and experiments show that the proposed technique has 100%, 93.60%, and 87.19% network availability by 100% packet delivery when 1, 2 and 3 routers are defunct or intentionally disabled. The algorithm provides adaptivity and it is lightweight, requiring one and two virtual channels along the X and Y dimension, respectively.
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