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- Ortiz, Gabriel, 1990, et al.
(author)
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A Framework for a Relative Real-Time Tracking System Based on Ultra-Wideband Technology
- 2018
-
In: IEEE Workshop on Positioning, Navigation and Communications (WPNC). ; 2018-January
-
Conference paper (peer-reviewed)abstract
- The growing number of applications in automated robots and vehicles has increased the demand for positioning, locating, and tracking systems. The majority of the current methods are based on machine vision systems and require a continuous direct line of sight (LOS) between the tracking device and the target for carrying out the desired functionalities. This limits the possible applications and makes them vulnerable to disturbances. The method presented in this paper aims to remove the continuous LOS requirement and allow for an omnidi- rectional and accurate tracking method using ultra-wideband (UWB) technology. This is achieved by placing a set of anchors within a short distance of one another on a device capable of movement that can keep track of the position of a target; this is in contrast to regular indoor positioning systems where a target monitors its own position in relation to a set of fixed reference anchors placed at a large distance apart. The new approach is referred to as the flipped anchors topology. The results show that the proposed topology is suitable for positioning, tracking and following applications that require a high degree of accuracy at short distances with the possibility of removing the continuous direct LOS requirement.
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| 33. |
- Ortiz, Gabriel, 1990, et al.
(author)
-
Instruction level energy model for the Adapteva Epiphany multi-core processor
- 2017
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In: 14th ACM International Conference on Computing Frontiers, CF 2017, Siena, Italy, 15-17 May 2017. - New York, NY, USA : ACM. - 9781450344876 ; , s. 380-384
-
Conference paper (peer-reviewed)abstract
- Processor energy models can be used by developers to estimate, without the need of hardware implementation or additional measurement setups, the power consumption of so ware applications. Furthermore, these energy models can be used for energy-aware compiler optimization. is paper presents a measurement-based instruction-level energy characterization for the Adapteva Epiphany processor, which is a 16-core shared-memory architecture connected by a 2D network-on-chip. Based on a number of microbenchmarks, the instruction-level characterization was used to build an energy model that includes essential Epiphany instructions such as remote memory loads and stores. To validate the model, an FFT application was developed. is validation showed that the energy estimated by the model is within 0.4% of the measured energy.
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| 34. |
- Peter, Kenneth, et al.
(author)
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Hardware considerations for selection networks
- 2019
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In: IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC. - 2324-8440 .- 2324-8432. ; 2019-October, s. 40-45
-
Conference paper (peer-reviewed)abstract
- The selection operation is a central part of a soft-decision error-correction algorithm, which is important for high-performance communication networks. High symbol rates and power-dissipation limitations motivate hardware implementation as a comparator network. We use industry-standard tools to investigate VLSI hardware implementation of selection networks with up to 512 inputs. We find theoretical network depth and size to be poor predictors of hardware performance. In a 65-nm process, we find that our novel half-life network is competitive with and in some cases superior to Zazon-Ivry’s pairwise and odd/even selection networks, for delay, area, and energy per selection operation.
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| 35. |
- Ryman, Erik J, 1982, et al.
(author)
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1.6 GHz Low-Power Cross-Correlator System Enabling Geostationary Earth Orbit Aperture Synthesis
- 2014
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In: IEEE Journal of Solid-State Circuits. - : Institute of Electrical and Electronics Engineers (IEEE). - 0018-9200 .- 1558-173X. ; 49:11, s. 2720-2729
-
Journal article (peer-reviewed)abstract
- We present a 64-channel cross-correlator system for space-borne synthetic aperture imaging. Two different types of ASICs were developed to fit into this system: An 8-channel comparator ASIC implemented in a 130 nm SiGe BiCMOS process technology performs A/D conversion, while a single 64-channel digital cross-correlator ASIC implemented in a 65 nm CMOS process performs the signal processing. The digital ASIC handles 2016 cross-correlations at up to 3.6 GS/s and has a power dissipation of only 0.13 mW/correlation/GHz at a supply voltage of 1 V. The comparator ASIC can handle sample rates of at least 4.5 GS/s with a power dissipation of 47 mW/channel or 1 GS/s with a power dissipation of 17 mW/channel. The assembled system consists of a single board measuring a mere 136 x 136 mm(2) and weighing only 135 g. The assembled system demonstrates crosstalk of 0.04% between neighboring channels and stability of 800 s. We provide ASIC and system-board measurement results that demonstrate that aperture synthesis can be a viable approach for Earth observation from a geostationary Earth orbit.
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| 36. |
- Ryman, Erik J, 1982, et al.
(author)
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3.6-GHz 0.2-mW/ch/GHz 65-nm Cross-Correlator for Synthetic Aperture Radiometry
- 2011
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In: Proceedings of the Custom Integrated Circuits Conference. - 0886-5930. - 9781457702228
-
Conference paper (peer-reviewed)abstract
- A high-speed low-power cross-correlator ASIC has been implemented in a 65-nm CMOS process for the purpose of synthetic aperture radiometry from geostationary orbitingearth observation satellites. The chip performs cross-correlation on all individual signal pairs from 64 digital 1-bit inputs, which amounts to 2016 individual cross-correlation products. The experimental evaluation, using a specially developed PCB, demonstrates that the 3-mm2 chip has a top performance of 3.6 GHz at a 1.2 V supply, at which it dissipates 790 mW.
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| 37. |
- Ryman, Erik J, 1982, et al.
(author)
-
A 3-GHz Reconfigurable 2/3-Level 96/48-Channel Cross-Correlator for Synthetic Aperture Radiometry
- 2017
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In: Proceedings of European Solid-State Circuits Conference (ESSCIRC). - 9781509050253
-
Conference paper (peer-reviewed)abstract
- We present a cross-correlator ASIC for synthetic aperture imaging of Earth’s atmosphere. Reconfigurability as a 2-level 96-channel or 3-level 48-channel cross-correlator provides adaptability to a wider array of applications. Implemented in a 65-nm CMOS process, the cross-correlator is capable of running at clock speeds of up to 3 GHz. In 2-level 96-channel mode, the cross-correlator consumes only 1.1 W at 2.5 GHz and 1.2 V, yielding a power efficiency of 96 μW/prod/GHz. The 450-Mb/s readout speed and double-buffering reduce blanking time of the interferometer system to a minimum.
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| 38. |
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| 39. |
- Ryman, Erik J, 1982, et al.
(author)
-
Custom versus Cell-Based ASIC Design for Many-Channel Correlators
- 2018
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In: IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation. - 1520-6130. - 9781538663189 ; 2018-October, s. 176-180
-
Conference paper (peer-reviewed)abstract
- While ASICs are efficient in terms of area utilization, performance, and power dissipation, ASIC design requires significant development resources. We compare two approaches to implementing ASIC correlators for interferometric imagers and spectrometers: The first approach, custom design, gives very high performance and area utilization, but is complex and time consuming. The second approach, cell-based design, reduces design time, but leads to lower performance and area utilization. In our evaluation, we consider two different correlator architectures: Autocorrelators for spectrometry, and cross-correlators for synthetic aperture imaging. Based on both 65-nm CMOS and 28-nm FD-SOI process technologies, our results show that for implementations for a limited number of channels, the cell-based approach may prove useful since it offers relatively short development time while still providing acceptable area utilization and performance. For larger designs, however, the area overhead of cell-based design becomes a major concern, especially for autocorrelator architectures.
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| 40. |
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