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| 2. |
- Behnam, Moris, et al.
(författare)
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Towards an efficient approach for resource sharing in real-time multiprocessor systems
- 2011
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Ingår i: 2011 6th IEEE International Symposium on Industrial and Embedded Systems. - Västerås : IEEE. - 9781612848181 - 9781612848198 ; , s. 99-102, s. 99-102
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Konferensbidrag (refereegranskat)abstract
- Supporting resource sharing in multiprocessor architectures is one of the major problems that limit the potential performance benefits of using such architectures for real-time systems. Many approaches and algorithms have been proposed to support resource sharing, however, most of them impose either high blocking times on tasks or require a large memory allocation. In this paper we investigate the possibility of combining the lock-based approaches and wait-free approaches (using multiple buffers) in order to decrease both the blocking times that may affect the schedulability of tasks and the required memory. To achieve this, we propose a solution based on evaluating the maximum allowed blocking time on each task according to the schedulability analysis, and then find the minimum memory allocation for each resource that limits the blocking times on tasks to be less than the maximum allowed blocking times.
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| 3. |
- Keskin, U., et al.
(författare)
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An engineering approach to synchronization based on overrun for compositional real-time systems
- 2011
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Ingår i: SIES 2011 - 6th IEEE International Symposium on Industrial Embedded Systems, Conference Proceedings. - 9781612848204 ; , s. 274-283
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Konferensbidrag (refereegranskat)abstract
- Hierarchical scheduling frameworks (HSFs) provide means for composing complex real-time systems from well-defined independently developed and analyzed subsystems. To support shared logical resources requiring mutual exclusive access in two-level HSFs, overrun without payback has been proposed as a mechanism to prevent budget depletion during resource access arbitrated by the stack resource policy (SRP). In this paper, we revisit the global schedulability analysis of synchronization protocols based on SRP and overrun without payback for fixed-priority scheduled HSFs. We derive a new global schedulability analysis based on the observation that the overrun budget is merely meant to prevent budget depletion during global resource access. The deadline of a subsystem therefore only needs to hold for its normal budget rather than the sum of the normal and overrun budget. Our novel analysis is considerably simpler than an earlier, initially improved analysis, which improved both the original local and global schedulability analyses. We evaluate the new analysis based on an extensive simulation study and compare the results with the existing analysis. Our simplified analysis does not significantly affect schedulability compared to the initially improved analysis. It is therefore proposed as a preferable engineering approach to synchronization protocols for compositional real-time systems. We accordingly present the implementation of our improvement in an OSEK-compliant real-time operating system to sketch its applicability in today's industrial automotive standards. Both implementation and run-time overheads are discussed providing measured results1. © 2011 IEEE.
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| 4. |
- Khalilzad, Nima Moghaddami, et al.
(författare)
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Towards adaptive hierarchical scheduling of overloaded real-time systems
- 2011
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Ingår i: SIES 2011 - 6th IEEE International Symposium on Industrial Embedded Systems, Conference Proceedings. - 9781612848204 ; , s. 39-42
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Konferensbidrag (refereegranskat)abstract
- In a hierarchical scheduling framework, a resource can be shared among modules with different criticality levels. In our recently introduced adaptive hierarchical scheduling framework, modules receive a dynamic portion of the CPU during run-time. While providing temporal isolation is one of the main advantages of hierarchical scheduling, in an adaptive framework, for example when the CPU is overloaded, the higher priority modules can violate timing guarantees of the lower priority modules. However, the priorities of modules are assigned based on parameters other than the module criticality levels. For example the priority is often assigned according to periods and deadlines of tasks to increase the CPU utilization assuming static systems, i.e. modules parameters do not change during runtime. In an overload situation the high criticality modules should be superior to the low criticality modules in receiving resources. In this paper, extending our adaptive framework, we propose two techniques for controlling the CPU distribution among modules in an overload situation. We are taking another step towards having a complete adaptive hierarchical scheduling framework by incorporating an overload controller into our framework.
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| 5. |
- Kraft, Johan, et al.
(författare)
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Continuous Constant-Memory Monitoring of Embedded Software Timing
- 2011
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Ingår i: 2nd International Workshop on Analysis Tools and Methodologies for Embedded and Real-time Systems (WATERS'11), satellite workshop of EUROMICRO Conference on Real-Time Systems (ECRTS'11).
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Konferensbidrag (refereegranskat)abstract
- A method is presented for generating statistical models of timing data continuously over very long monitoring sessions. This method is intended for memory-efficient runtime modeling of timing properties in embedded software systems, such as execution times or inter-arrival times, but is a quite generic method that should be applicable for other purposes and domains as well. Specifically, we intend to use this method as a component in automatic generation of simulation models for probabilistic timing analysis of complex embedded software systems. Given a stream of data as input, this method gradually builds up a statistical model capturing the approximate distribution of the data. The method uses a modest and fixed amount of on-target RAM, decided by the desired accuracy of the model, and allows for long monitoring sessions covering billions of data points. The paper presents the motivation, algorithm, a prototype implementation and evaluation using real execution time data from an ARM7 microcontroller.
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| 6. |
- Kraft, Johan, et al.
(författare)
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Software Maintenance Research in the PROGRESS Project for Predictable Embedded Software Systems
- 2011
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Ingår i: 15th European Conference on Software Maintenance and Reengineering (CSMR'11). - Los Alamitos : IEEE Computer Society. - 9780769543437 ; , s. 335-338
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Konferensbidrag (refereegranskat)abstract
- PROGRESS is a project and strategic research centre at Malardalen University in Sweden that is funded for 2006-2010 by the Swedish Foundation for Strategic Research (SSF). PROGRESS research targets embedded software in the vehicular, automation, and telecom domains, focusing on the areas of component technology, verification and analysis for predictability, predictable execution, as well as reuse and maintenance of legacy embedded software. We first describe the funding, organization and research areas of PROGRESS, and then give several examples of PROGRESS research that addresses maintenance of legacy embedded software with the goal to improve program comprehension, quality assurance, and debugging. Specifically, we describe research in tracing and trace visualization, impact analysis of temporal behavior, slicing, and system-specific static analyses.
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| 7. |
- Lu, Yue, et al.
(författare)
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A New Way about using Statistical Analysis of Worst-Case Execution Times
- 2011
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Ingår i: ACM SIGBED Review. - : Association for Computing Machinery (ACM). - 1551-3688. ; 8:3, s. 11-14
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, we revisit the problem of using Extreme Value Theory (EVT) in the Worst-Case Execution Time (WCET) analysis of the programs running on a single processor. Our proposed statistical WCET analysis method consists of a novel sampling mechanism tackling with some problems that hindered the application of using EVT in the context, and a statistical inference about computation of a WCET estimate of the target program. To be specific, the presented sampling mechanism takes analysis samples from the target program based around end-to-end measurements. Next, the statistical inference using EVT together with other statistical techniques, analyzes such timing traces which contain the execution time data of the program, to compute a WCET estimate with a certain predictable probability of being exceeded.
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| 8. |
- Lu, Yue, et al.
(författare)
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A statistical approach to simulation model validation in response-time analysis of complex real-time embedded systems
- 2011
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Ingår i: Proceedings of the ACM Symposium on Applied Computing 2011. - New York, NY, USA : ACM. - 9781450301138 ; , s. 711-716
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Konferensbidrag (refereegranskat)abstract
- As simulation-based analysis methods make few restrictions on the system design and scale to very large and complex systems, they are widely used in, e.g., timing analysis of complex real-time embedded systems (CRTES) in industrial circles. However, before such methods are used, the analysis simulation models have to be validated in order to assess if they represent the actual system or not, which also matters to the confidence in the simulation results. This paper presents a statistical approach to validation of temporal simulation models extracted from CRTES, by introducing existing mature statistical hypothesis tests to the context. Moreover, our evaluation using simulation models depicting a fictive but representative industrial robotic control system indicates that the proposed method can successfully identify temporal differences between different simulation models, hence it has the potential to be considered as an effective simulation model validation technique. © 2011 ACM.
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| 9. |
- Lu, Yue, et al.
(författare)
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A statistical response-time analysis of complex real-time embedded systems by using timing traces
- 2011
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Ingår i: SIES 2011 - 6th IEEE International Symposium on Industrial Embedded Systems, Conference Proceedings. - 9781612848204 ; , s. 43-46
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Konferensbidrag (refereegranskat)abstract
- Real-time embedded systems are becoming ever more complex, and we are reaching the stage where even if static Response-Time Analysis (RTA) was feasible from a cost and technical perspective, the results are overly pessimistic making them less useful to the practitioner. When combined with the fact that most timing analysis tends to be statistical in nature, this suggests there should be a move towardstatistical RTA. However, to make such analysis useful, it is imperative that we have evidence that the statistical RTA and the information analyzed is sufficiently accurate. In this paper we present and validatea technique for statistical RTA that can cope with systems that are complex from both a size and tasks' dependencies perspective. This claim is backed up by our evaluation using information from realindustrial control systems.
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| 10. |
- Lu, Yue, et al.
(författare)
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A Trace-Based Statistical Worst-Case Execution Time Analysis of Component-Based Real-Time Embedded Systems
- 2011
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Ingår i: 2011 IEEE 16TH CONFERENCE ON EMERGING TECHNOLOGIES AND FACTORY AUTOMATION (ETFA). - New York : IEEE. - 9781457700187
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Konferensbidrag (refereegranskat)abstract
- This paper describes the tool support for a framework for performing statistical WCET analysis of real-time embedded systems by using bootstrapping sampling and Extreme Value Theory (EVT). To be specific, bootstrapping sampling is used to generate timing traces, which not only fulfill the requirements given by statistics and probability theory, but also are robust to use in the context of estimating the WCET of programs. Next, our proposed statistical inference uses EVT to analyze such timing traces, and computes a WCET estimate of the target program, pertaining to a given predictable probability. The evaluation results show that our proposed method could have the potential of being able to provide a tighter upper bound on the WCET estimate of the programs under analysis, when compared to the estimates given by the referenced WCET analysis methods.
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