| 311. |
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| 312. |
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| 313. |
- Tammemäe, Kalle, et al.
(författare)
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AKKA: A Tool-kit for Cosynthesis and Prototyping
- 1996
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Ingår i: Hardware-Software Cosynthesis for Reconfigurable Systems, IEE Colloquium, Bristol 22 Feb. 1996. - : IEE. ; , s. 8/1-8/8
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- Shortened design and life time of embedded systems has motivated active research in HW/SW co-design area, together with evolution of relatively long-life of reconfigurable HW. In this paper we present Akka1[1][2] - a set of tools for design space exploration, co-simulation and co-synthesis with two industrial examples from the telecommunication field - Maintenance functionality of the ATM protocol and Channel decoder functionality of a D-AMPS base station. For fast prototyping we have selected Xilinx XC4013 FPGA based board from Virtual Computer Corporation. The board is connected to the system bus (SBus) of the host computer.
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| 314. |
- Tatas, K., et al.
(författare)
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Designing 2D and 3D network-on-chip architectures
- 2014
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Bok (övrigt vetenskapligt/konstnärligt)abstract
- This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliability. Case studies are used to illuminate new design methodologies.
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| 315. |
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| 316. |
- Thid, Rikard, et al.
(författare)
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Evaluating NoC communication backbones with simulation
- 2003
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Ingår i: Proceedings of the 21th NorChip Conference. - : IEEE conference proceedings. ; , s. 27-30
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Konferensbidrag (refereegranskat)abstract
- This paper describes a Network on Chip simulatorthat was developed to evaluate our NoC architecture Nostrum.It is shown how SystemC’s features for communicationrefinement is used to make a highly flexible simulator.The simulator is reconfigurable so that it is possibleto try different NoC platforms and different mappingsof workloads. In addition to the modeling of our Nostrumarchitecture, a bus-based architecture is modeled aswell, and the performance for a simple workload modelis compared.
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| 317. |
- Thid, Rikard, et al.
(författare)
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Flexible bus and NoC performance analysis with configurable synthetic workloads
- 2006
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Ingår i: DSD 2006. - 0769526098 ; , s. 681-688
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Konferensbidrag (refereegranskat)abstract
- We present a flexible method for bus and network on chip performance analysis, which is based on the adaptation of workload models to resemble various applications. Our analysis method assists in the selection of a communication infrastructure early in the design process. The method uses (1) synthetic workload models which are similar to timed Petri nets and (2) the b-model for self-similar workloads. This allows the exploration of larger portions of the design space than possible with traditional stochastic models. The method is illustrated with tutorial examples where both a No C and a bus based platform are analyzed.
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| 318. |
- Vitkovski, Arsenij, et al.
(författare)
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Low-power and error coding for network-on-chip traffic
- 2004
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Ingår i: 22ND NORCHIP CONFERENCE, PROCEEDINGS. - NEW YORK : IEEE. - 0780385101 ; , s. 20-23
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Konferensbidrag (refereegranskat)abstract
- The goals of this paper are to explore adaptability of low-power coding techniques, and estimate error coding overheads for Network-on-Chip (NoC) bus interconnections. Our simulations show that bus-invert encoding and partial bus invert encoding are not efficient due to their large overheads. On the other hand, implementation of error protection codes in the switch has only a small influence on both power consumption and time delay.
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| 319. |
- Vitkovski, A., et al.
(författare)
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Low-power and error protection coding for network-on-chip traffic
- 2008
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Ingår i: IET Computers and Digital Techniques. - : Institution of Engineering and Technology (IET). - 1751-8601. ; 2:6, s. 483-492
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Tidskriftsartikel (refereegranskat)abstract
- The power consumption of the network-on-chip communication backbone is explored and the effectiveness of low-power encoding and error protection techniques is analysed. For the switch under the study, a Nostrum defective routing switch, simulations and power analysis suggest that only a minor fraction of the power is dissipated in the logic blocks, whereas the major part is due to the interconnection wires. The authors have investigated a number of low-power and data protection mechanisms and studied their impact on power consumption of the whole network. The bus-invert encoding scheme and a limited set of Hamming data protection codes have been implemented on both data link and at the network layer. However, it turned out that all low-power data encoding schemes have little potential to decrease power consumption due to the significant overhead. On the other hand, error protection mechanisms have a significant potential to decrease power consumption because they allow to operate the network at a lower voltage. The authors' experiments show a 20% decrease of power consumption for a given error rate and for a given performance.
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| 320. |
- Wang, Junshi, et al.
(författare)
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Efficient Design-for-Test Approach for Networks-on-Chip
- 2019
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Ingår i: IEEE Transactions on Computers. - : IEEE Computer Society Digital Library. - 0018-9340 .- 1557-9956. ; 68:2, s. 198-213
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Tidskriftsartikel (refereegranskat)abstract
- To achieve high reliability in on-chip networks, it is necessary to test the network continuously with Built-in Self-Tests (BIST) so that the faults can be detected quickly and the number of affected packets can be minimized. However, BISTcauses significant performance loss due to data dependencies. We propose EsyTest, a comprehensive test strategy with minimized influence on system performance. EsyTest tests the data path and the control path separately. The data path test starts periodically, but the actual test performs in the free time slots to avoid deactivating the router for testing. A reconfigurable router architecture and an adaptive fault-tolerant routing algorithm are proposed to guarantee the access to the processing core when the associated router is under test. During the whole test procedure of the network, all processing cores are accessible, and thus the system performance is maintained during the test. At the same time, EsyTest provides a full test coverage for the NoC and a better hardware compatibility comparing with the existing test strategies. Under the PARSEC benchmark and different test frequencies, the execution time increases less than 5 percent at the cost of 9.9 percent more area and 4.6 percent more power in comparison with the execution where no test procedure is applied.
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