| 181. |
- Malik, Omer, et al.
(författare)
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High Level Synthesis Framework for a Coarse Grain Reconfigurable Architecture
- 2010
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Ingår i: 28th Norchip Conference, NORCHIP 2010. - 9781424489732 ; , s. 5669439-
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Konferensbidrag (refereegranskat)abstract
- A High Level Synthesis Framework for mapping DSP algorithms on a Coarse Grain Reconfigurable Architecture is presented. Behavioral specification of the algorithm in C is specified with pragmas in comments and the tool generates configware after performing timing and synchronization synthesis. Pragmas identify SIMD type concurrency and sweep the architectural space with allocation and binding annotations to produce implementations from fully serial to fully parallel. This allows user to stay at algorithmic level and guide the HLS tool to search a restricted architectural space bounded by the pragmas thus making the synthesis process more efficient and predictable.
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| 182. |
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| 183. |
- Malik, Omer, et al.
(författare)
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Synchronizing distributed state machines in a coarse grain reconfigurable architecture
- 2011
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Ingår i: 2011 International Symposium on System on Chip, SoC 2011. - 9781457706721 ; , s. 128-135
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Konferensbidrag (refereegranskat)abstract
- This work presents methodology for synchronizing distributed FSMs (Finite State Machines) which are generated while implementing different algorithms on a coarse grain reconfigurable architecture. These FSMs interact with each other while executing algorithms and they are dependent upon each other; thus they need to be synchronized with each other for performing correct execution. The algorithms presented in this paper makes appropriate use of different strategies available for synchronizing these FSMs. The tool hides all sorts of low level details from the Programmer. It lets the designer focus on the details of algorithm (at higher level of abstraction) and cycle by cycle timings are resolved automatically.
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| 184. |
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| 185. |
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| 186. |
- Meincke, Thomas, et al.
(författare)
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Globally asynchronous locally synchronous architecture for large high-performance ASICs
- 1999
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Ingår i: ; 2, s. 512-515
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Konferensbidrag (refereegranskat)abstract
- Clock nets are the major source of power consumption in large, high-performance ASICs and a design bottleneck when it comes to tolerable clock skew. A way to obviate the global clock net is to partition the design into large synchronous blocks each having its own clock. Data with other blocks is exchanged asynchronously using handshake signals. Adopting such a strategy requires a methodology that supports: 1) a partitioning method dividing a design into the number of synchronous blocks such that the gain due to global clock net removal exceeds the communication overhead and 2) synthesis of handshake protocols to implement the data transfer between synchronous blocks. We describe this methodology and present results of applying it to a realistic design done in 0.25 micron, ranging in operating frequencies from 20 MHz to 1 GHz. The results show that the net power savings compared to fully synchronous designs are on an average about 30%
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| 187. |
- Mirsalari, Seyed Ahmad, et al.
(författare)
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Optimizing Self-Organizing Maps for Bacterial Genome Identification on Parallel Ultra-Low-Power Platforms
- 2023
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Ingår i: ICECS 2023 - 2023 30th IEEE International Conference on Electronics, Circuits and Systems: Technosapiens for Saving Humanity. - : Institute of Electrical and Electronics Engineers (IEEE).
-
Konferensbidrag (refereegranskat)abstract
- Pathogenic bacteria significantly threaten human health, highlighting the need for precise and efficient methods for swiftly identifying bacterial species. This paper addresses the challenges associated with performing genomics computations for pathogen identification on embedded systems with limited computational power. We propose an optimized implementation of Self-Organizing Maps (SOMs) targeting a parallel ultra-low-power platform based on the RISC-V instruction set architecture. We propose two mapping methods for implementing the SOM algorithm on a parallel cluster, coupled with software techniques to improve the throughput. Orthogonally to parallelization, we investigate the impact of smaller-than-32-bit floating-point formats (smallFloats) on energy savings, precision, and performance. Our experimental results show that all smallFloat formats exhibit a 100% classification accuracy. The parallel variants achieve a speed-up of 1.98 × , 3.79 ×, and 6.83 × on 2, 4, and 8 cores, respectively. Comparing our design with a 16-bit fixed-point implementation on a coarse grain reconfigurable architecture (CGRA), the FP8 implementation achieves, on average, 1. 42 × energy efficiency, 1. 51 × speedup, and a 50% reduction in memory footprint compared to CGRA. Furthermore, FP8 vectorization increases the average speed-up by 2.5 ×.
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| 188. |
- Ngyen, T., et al.
(författare)
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FIST : A framework to interleave spiking neural networks on CGRAs
- 2015
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Ingår i: Proceedings - 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2015. - : IEEE. ; , s. 751-758
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Konferensbidrag (refereegranskat)abstract
- Coarse Grained Reconfigurable Architectures (CGRAs) are emerging as enabling platforms to meet the high performance demanded by modern embedded applications. In many application domains (e.g. robotics and cognitive embedded systems), the CGRAs are required to simultaneously host processing (e.g. Audio/video acquisition) and estimation (e.g. audio/video/image recognition) tasks. Recent works have revealed that the efficiency and scalability of the estimation algorithms can be significantly improved by using neural networks. However, existing CGRAs commonly employ homogeneous processing resources for both the tasks. To realize the best of both the worlds (conventional processing and neural networks), we present FIST. FIST allows the processing elements and the network to dynamically morph into either conventional CGRA or a neural network, depending on the hosted application. We have chosen the DRRA as a vehicle to study the feasibility and overheads of our approach. Synthesis results reveal that the proposed enhancements incur negligible overheads (4.4% area and 9.1% power) compared to the original DRRA cell.
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| 189. |
- Nidhi, U., et al.
(författare)
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High performance 3D-FFT implementation
- 2013
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Ingår i: Circuits and Systems (ISCAS), 2013 IEEE International Symposium on. - : IEEE. - 9781467357609 ; , s. 2227-2230
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Konferensbidrag (refereegranskat)abstract
- 3D FFT is a very data and compute intensive kernel encountered in many applications. We report a high performance design and implementation of 3D-FFT on a CGRA which supports partial reconfiguration. The hardware software multi clock design uses dynamic reconfiguration to reduce the required communication bandwidth to achieve a sustained throughput of 40 GOPS on a wordsize of 48 bits. Performance metrics including overheads and speed over software for implementations of up to 256 point 3D-FFT have been presented in the paper.
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| 190. |
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