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- Al-Obaidi, Mohammed, et al.
(author)
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Hardware Acceleration of the Robust Header Compression (RoHC) Algorithm
- 2013
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In: 2013 IEEE International Symposium on Circuits and Systems (ISCAS). - 2158-1525 .- 0271-4310. - 9781467357609 - 9781467357623 ; , s. 293-296
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Conference paper (peer-reviewed)abstract
- In LTE base-stations, RoHC is a processingintensive algorithm that may limit the system from serving a large number of users when it is used to compress the VoIP packets of mobile traffic. In this paper, a hardware-software and a full-hardware solution are proposed to accelerate the RoHC compression algorithm in LTE base-stations and enhance the system throughput and capacity. Results for both solutions are discussed and compared with respect to design metrics like throughput, capacity, power consumption, and hardware resources. This comparison is instrumental in taking architectural level trade-off decisions in-order to meet the present day requirements and also be ready to support a future evolution. In terms of throughput, a gain of 20% (6250 packets/sec) is achieved in the HW-SW implementation by accelerating the Cyclic Redundancy Check (CRC) and the Least Significant Bit (LSB) encoding in hardware. The full-HW implementation leads to a throughput of 45 times (244000 packets/sec) compared to the SW-Only implementation. The full-HW solution consumes more Adaptive Look-Up Tables (7477 ALUTs) compared to the HW-SW solution (2614 ALUTs) when synthesized on Altera’s Arria II GX FPGA.
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| 4. |
- Berkeman, Anders, et al.
(author)
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A configurable divider using digit recurrence
- 2003
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In: Proceedings - IEEE International Symposium on Circuits and Systems. - 2158-1525 .- 0271-4310. ; 5, s. 333-336
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Conference paper (peer-reviewed)abstract
- The division operation is essential in many digital signal processing algorithms. For a hardware implementation, the requirements and constraints on the divider circuit differ significantly with different applications. Therefore, it is not possible to design one divider component having optimal performance and cost for all target applications. Instead, the presented divider has a modular architecture, based on instantiation of small efficient divider sub-blocks. The configuration of the divider architecture is set by a number of parameters controlling wordlength, number of quotient bits, number of clock cycles per operation, and fixed or floating point operation. Digit recurrence algorithms with carry save arithmetic and on-the-fly two's complement output quotient conversion are used to make the sub-blocks small, fast and power efficient, The modularity gives the designer freedom to elaborate different parameters to explore the design space. Two applications using the proposed divider are presented. Furthermore, an example divider circuit has been fabricated and performance measurements are included.
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| 6. |
- Berkeman, Anders, et al.
(author)
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A low logic depth complex multiplier
- 1998
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In: ; , s. 204-207
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Conference paper (peer-reviewed)abstract
- A complex multiplier has been designed for use in a pipelined fast fourier transform processor. The performance in terms of throughput of the processor is limited by the multiplication. Therefore, the multiplier is optimized to make the input to output delay as short as possible. A new architecture based on distributed arithmetic and Wallace-trees has been developed and is compared to a previous multiplier realized as a regular distributed arithmetic array. The simulated gain in speed for the presented multiplier is about 100%. For verification, the multiplier is fabricated in a three metal-layer 0.5µ CMOS process using a standard cell library. The fabricated multiplier chip has been functionally verified.
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| 9. |
- Berkeman, Anders, et al.
(author)
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Co-optimization of FFT and FIR in a delayless acoustic echo canceller implementation
- 2000
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In: [Host publication title missing]. - 0780354826 ; 5, s. 241-244
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Conference paper (peer-reviewed)abstract
- In application specific implementation of digital signal processing algorithms optimization is important for a low power solution, not only on block level but also between blocks. This paper presents a co-optimization of a fast Fourier transform and a finite impulse response filter in a silicon implementation of an acoustic echo. The optimization gain can be measured in the number of operations and memory accesses performed per second, and therefore processing power. The optimization can also be applied to other algorithms with a similar constellation of Fourier transforms and finite impulse response filters
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| 10. |
- Berkeman, Anders, et al.
(author)
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Implementation Issues for acoustic echo cancellers
- 1999
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In: [Host publication title missing]. - 0780354915 ; , s. 97-100
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Conference paper (peer-reviewed)abstract
- The high computational complexity of acoustic echo cancellation algorithms requires application specific implementations to sustain real time signal processing with affordable power consumption. This is especially true for systems where a delayless approach is considered important, e.g. wireless communication systems. The proposed paper presents architectural considerations to reach a feasible hardware solution.
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