| 61. |
- Farahini, Nasim, et al.
(författare)
-
Distributed Runtime Computation of Constraints for Multiple Inner Loops
- 2013
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Ingår i: Proceedings - 16th Euromicro Conference on Digital System Design, DSD 2013. - New York : IEEE. - 9780769550749 ; , s. 389-395
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Konferensbidrag (refereegranskat)abstract
- This paper presents hardware solution for runtime computation of loop constraints and synchronizing delays for multiple inner loops in parallel distributed implementation of digital signal processing sub-systems. Methods to map and generate the runtime computation code for loop constraints and synchronizing delays are also presented. Compared to the traditional methods, the proposed solution achieves 55% average code compaction and 32.7% average performance improvement. The solution has modest hardware cost that increases linearly with the dimension of the architecture and has no performance penalty. Results from multiple realistic examples are presented, analyzed and compared to the traditional methods.
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| 62. |
- Farahini, Nasim, et al.
(författare)
-
Parallel distributed scalable runtime address generation scheme for a coarse grain reconfigurable computation and storage fabric
- 2014
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Ingår i: Microprocessors and microsystems. - : Elsevier BV. - 0141-9331 .- 1872-9436. ; 38:8, s. 788-802
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a hardware based solution for a scalable runtime address generation scheme for DSP applications mapped to a parallel distributed coarse grain reconfigurable computation and storage fabric. The scheme can also deal with non-affine functions of multiple variables that typically correspond to multiple nested loops. The key innovation is the judicious use of two categories of address generation resources. The first category of resource is the low cost AGU that generates addresses for given address bounds for affine functions of up to two variables. Such low cost AGUs are distributed and associated with every read/write port in the distributed memory architecture. The second category of resource is relatively more complex but is also distributed but shared among a few storage units and is capable of handling more complex address generation requirements like dynamic computation of address bounds that are then used to configure the AGUs, transformation of non-affine functions to affine function by computing the affine factor outside the loop, etc. The runtime computation of the address constraints results in negligibly small overhead in latency, area and energy while it provides substantial reduction in program storage, reconfiguration agility and energy compared to the prevalent pre-computation of address constraints. The efficacy of the proposed method has been validated against the prevalent address generation schemes for a set of six realistic DSP functions. Compared to the pre-computation method, the proposed solution achieved 75% average code compaction and compared to the centralized runtime address generation scheme, the proposed solution achieved 32.7% average performance improvement.
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| 63. |
- Farahini, Nasim, et al.
(författare)
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Physical Design Aware System Level Synthesis of Hardware
- 2015
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Ingår i: Proceedings - Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2015. - : IEEE. ; , s. 141-148
-
Konferensbidrag (refereegranskat)abstract
- In spite of decades of research, only a small percentage of hardware is designed using high-level synthesis because of the large gap between the abstraction levels of standard cells and algorithmic level. We propose a grid-based regular physical design platform composed of large grain hardened building blocks called SiLago blocks. This platform is divided into regions which are specialized for different functionalities like computation, storage, system control, etc. The characterized micro-architectural operations of the SiLago platform serve as the interface to meet-in-the-middle high-level and system-level syntheses framework. This framework was used to generate three hardware macro instances, derived from SiLago platform for three applications from signal processing domain. Results show two orders of magnitude improvements in efficiency of the system-level design space exploration and synthesis time, with average loss in design quality of 18% for energy and 54% for area compared to the commercial SOC flow.
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| 64. |
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| 65. |
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| 66. |
- Hellberg, Lars, et al.
(författare)
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System oriented VLSI curriculum at KTH
- 1997
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Ingår i: ; , s. 57-59
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Konferensbidrag (refereegranskat)abstract
- This paper describes the restructuring of VLSI education at the Royal Institute of Technology (KTH). Changing needs of industry, advances in technology and design methodology has required a significant reorganization of VLSI education with combined emphasis on system issues and associated physical constraints. We present here a course structure which will address, in parallel fashion, the key design issues for future system products
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| 67. |
- Hemani, Ahmed, et al.
(författare)
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A neural net based Self Organising Scheduling Algorithm
- 1990
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Ingår i: Proceedings of the European Design Automation Conference. - : IEEE. - 0818620242 ; , s. 136-140
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Konferensbidrag (refereegranskat)abstract
- Scheduling is a crucial task in behavioural synthesis and aNp-hard optimisation problem. Neural net computationparadigms bring potential for efficient solutions to suchproblems. This paper presents a new scheduling algorithmbased on Kohonen’s rule for self organisation. The algorithmhas an inherent hill climbing mechanism, copeswith a comprehensive set of constraints and can be implementedon massively parallel structures. Its performanceon well known benchmark examples, presented in the paper,is on par with the best reported.
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| 68. |
- Hemani, Ahmed, et al.
(författare)
-
A structure of modern VLSI curriculum
- 1994
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Ingår i: ; , s. 204-208
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Konferensbidrag (refereegranskat)abstract
- This paper describes the restructuring of VLSI education at Royal Institute of Technology, Sweden. Changing needs of industry, advances in technology and design methodology has required a significant reorganisation of VLSI education with emphasis on system issues. This restructuring is not viewed as a one step process, rather as a continuous process including close interaction between education and research
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| 69. |
- Hemani, Ahmed, et al.
(författare)
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Application of high-level synthesis in an industrial project
- 1994
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Ingår i: VLSI Design, 1994., Proceedings of the Seventh International Conference on. ; , s. 5-10
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Konferensbidrag (refereegranskat)abstract
- This paper describes the use of high-level synthesis in conjunction with logic synthesis for designing an industrial product specified at system-level in behavioral VHDL and realized in FPGAs. The designers’ experiences from using the high-level synthesis tool and its interaction with the other tools are analyzed. Important problems were the handling of precise timing constraints and feedback of adequate technology information to the high-level synthesis
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| 70. |
- Hemani, Ahmed, et al.
(författare)
-
Cell placement by self-organisation
- 1990
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Ingår i: Neural Networks. - 0893-6080 .- 1879-2782. ; 3:4, s. 377-383
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Tidskriftsartikel (refereegranskat)
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