| 21. |
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| 22. |
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| 23. |
- Ezzeddine, Hussein, et al.
(författare)
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Validation of Pipelined Double-precision Floating Point operations in a multi-core environment implemented on FPGA using the ForSyDe/NoC system generator tool suite
- 2015
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Ingår i: NORCHIP 2014 - 32nd NORCHIP Conference. - 9781479954421
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Konferensbidrag (refereegranskat)abstract
- Testing HW IP Blocks in multi-core environments is difficult. This paper presents a case study where a SINE/COSINE implementation using Pipelined Double-precision operations is implemented in one node, and results are sent through the NoC to a target node for inspection. The purpose of the experiments are two-fold, a) to study how debugging in a multi-core environment can be done and b) to examine why the original SINE/COSINE implementation is generating wrong results. During the experiments, several test-methods are applied to validate the implementations until the Floating Point implementation are generating correct values. After eliminating all faults in the operations, the SINE/COSINE function still generates some residual algorithmic errors, coming from the way the function was implemented. However, the experiments show that these errors can be eliminated with the help of some simple trigonometric rales.
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| 24. |
- Fakih, Maher, et al.
(författare)
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Experimental Evaluation of SAFEPOWER Architecture for Safe and Power-Efficient Mixed-Criticality Systems
- 2019
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Ingår i: Journal of Low Power Electronics and Applications. - : MDPI AG. - 2079-9268. ; 9:1
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Tidskriftsartikel (refereegranskat)abstract
- With the ever-increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible. Even in safety-critical domains like railway and avionics, multicore processors are introduced, but under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such a System on Chip (SoC) is to enhance the way the SoC handles its power consumption. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC, which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power-saving methods in safety-critical domains yet. The EU project SAFEPOWER (Safe and secure mixed-criticality systems with low power requirements) targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality systems. This article provides an overview of the SAFEPOWER reference architecture for low-power mixed-criticality systems, which is the most important outcome of the project. Furthermore, the application of this reference architecture in novel railway interlocking and flight controller avionic systems was demonstrated, showing the capability to achieve power savings up to 37%, while still guaranteeing time-triggered task execution and time-triggered NoC-based communication.
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| 25. |
- Fakih, M., et al.
(författare)
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SAFEPOWER project : Architecture for safe and power-efficient mixed-criticality systems
- 2017
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Ingår i: Microprocessors and microsystems. - : Elsevier. - 0141-9331 .- 1872-9436. ; 52, s. 89-105
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Tidskriftsartikel (refereegranskat)abstract
- With the ever increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible without regarding their criticality. Even safety critical domains like railway and avionics apply these paradigms under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such System on Chip (SoC) is to enhance the way the SoC handles its power resources. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power saving methods in safety critical domains yet. The EU project SAFEPOWER1.
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| 26. |
- Hemani, Ahmed, et al.
(författare)
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High-level synthesis of control and memory intensive communication systems
- 1995
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Ingår i: ; , s. 185-191
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Konferensbidrag (refereegranskat)abstract
- Communication sub-systems that deal with switching, routing and protocol implementation often have their functionality dominated by control logic and interaction with memory. Synthesis of such Control and Memory Intensive Systems (hereafter abbreviated to CMISTs) poses demands that in the past have not been met satisfactorily by general purpose high-level synthesis (HLS) tools and have led to several research efforts to address these demands. In this paper we: characterise CMISTs from the synthesis viewpoint; present a synthesis methodology adapted for CMISTs; present the Operation and Maintenance (OAM) Protocol of the ATM, its modelling in VHDL and synthesis aspects of the VHDL model; present the results of applying the synthesis methodology to the OAM as a test case-the results are compared to that obtained using the not adapted general purpose High-level synthesis tool; prove the efficacy of the proposed synthesis methodology by applying it to an industrial design and comparing our results to the results from two commercial HLS tools and to the results obtained by designing manually at register-transfer level
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| 27. |
- Hemani, Ahmed, et al.
(författare)
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Lowering power consumption in clock by using globally asynchronous locally synchronous design style
- 1999
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Ingår i: Design Automation Conference, 1999. Proceedings. 36th. ; , s. 873-878
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Konferensbidrag (refereegranskat)abstract
- Power consumption in clock of large high performance VLSIs can be reduced by adopting globally asynchronous, locally synchronous design style (GALS). GALS has small overheads for the global asynchronous communication and local clock generation. We propose methods to (a) evaluate the benefits of GALS and account for its overheads, which can be used as the basis for partitioning the system into optimal number/size of synchronous blocks, and (b) automate the synthesis of the global asynchronous communication. Three realistic ASICs, ranging in complexity from 1 to 3 million gates, were used to evaluate GALS benefits and overheads. The results show an average power saving of about 70% in clock with negligible overheads
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| 28. |
- Hemani, Ahmed, et al.
(författare)
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Lowering Power Consumption in Clock by Using Globally Asynchronous Locally Synchronous Design Style
- 1999
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Ingår i: Proceedings of the 36th ACM/IEEE conference on Design automation. - New York, NY, USA : ACM. ; , s. 873-878
-
Konferensbidrag (refereegranskat)abstract
- Power consumption in clock of large high performance VLSIs can be reduced by adopting Globally Asynchronous, Locally Synchronous design style (GALS). GALS has small overheads for the global asynchronous communication and local clock generation. We propose methods to a) evaluate the benefits of GALS and account for its overheads, which can be used as the basis for partitioning the system into optimal number/size of synchronous blocks, and b) automate the synthesis of the global asynchronous communication. Three realistic ASICs, ranging in complexity from 1 to 3 million gates, were used to evaluate GALS benefits and overheads. The results show an average power saving of about 70% in clock with negligible overheads.
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| 29. |
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| 30. |
- Hemani, Ahmed, et al.
(författare)
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System level virtual prototyping of DSP ASICs using grammar based approach
- 1999
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Ingår i: Rapid System Prototyping, 1999. IEEE International Workshop on. ; , s. 166-171
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Konferensbidrag (refereegranskat)abstract
- DSP systems are often modeled using functional and bit-true level simulators, where it is not possible to validate the system level timing, control and configuration (SLTCC) of the product. In this paper, we present a methodology that adds SLTCC specified in grammar to functional models to create a rate true system level virtual prototype. The methodology is illustrated and benefits are quantified using two realistic examples
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