| 11. |
- Liu, Ming, et al.
(författare)
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Run-time Partial Reconfiguration Speed Investigation and Architectural Design Space Exploration
- 2009
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Ingår i: FPL 09. - 9781424438914 ; , s. 498-502
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Konferensbidrag (refereegranskat)abstract
- Run-time Partial Reconfiguration (PR) speed is significant in applications especially when fast IP core switching is required. In this paper, we propose to use Direct Memory Access (DMA), Master (MST) burst, and a dedicated Block RAM (BRAM) cache respectively to reduce the reconfiguration time. Based on the Xilinx PR technology and the Internal Configuration Access Port (ICAP) primitive in the FPGA fabric, we discuss multiple design architectures and thoroughly investigate their performance with measurements for different partial bitstream sizes. Compared to the reference OPB_HWICAP and XPS_HWICAP designs, experimental results show that DMA_HWICAP and MST_HWICAP reduce the reconfiguration time by one order of magnitude, with little resource consumption overhead. The BRAM_HWICAP design can even approach the reconfiguration speed limit of the ICAP primitive at the cost of large Block RAM utilization.
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| 12. |
- Liu, Ming, et al.
(författare)
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System-on-an-FPGA Design for Real-time Particle Track Recognition and Reconstruction in Physics Experiments
- 2008
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Ingår i: 11TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN - ARCHITECTURES, METHODS AND TOOLS. - LOS ALAMITOS : IEEE COMPUTER SOC. ; , s. 599-605
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Konferensbidrag (refereegranskat)abstract
- In particle physics experiments, the momenta of charged particles are studied by observing their deflection in a magnetic field. Dedicated detectors measure the particle tracks and complex algorithms are required for track recognition and reconstruction. This CPU-intensive task is usually implemented as off-line software running on PC clusters. In this paper we present a system-on-chip design for the track recognition and reconstruction based on modern FPGA technologies. The basic principle of the algorithm is polled from software into the FPGA fabric. The fundamental architecture of the tracking processor is described in detail. Working as processing engines in compute nodes, the tracking processor contributes to recognize potential track candidates in real-time and promotes the selection efficiency of the data acquisition and trigger system. Our design study shows that the tracking module can be integrated in a single Xilinx Virtex-4 FX60 FPGA. The processing capability of the design is about 16.7K sub-events per second per module with our experimental setup, which achieves 20 times speedup compared to the software implementation.
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| 13. |
- Liu, Ming, et al.
(författare)
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Trigger algorithm development on FPGA-based Compute Nodes
- 2009
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Ingår i: 2009 16th IEEE-NPSS Real Time Conference. - New York : IEEE. - 9781424457960 ; , s. 478-484
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Konferensbidrag (refereegranskat)abstract
- Based on the ATCA computation architecture and Compute Nodes (CN), investigation and implementation work has been being executed for HADES and PANDA trigger algorithms. We present our designs for HADES track reconstruction processing, Cherenkov ring recognition, Time-Of-Flight processing, electromagnetic shower recognition.. and the PANDA straw tube tracking algorithm. They will appear as co-processors in the uniform system design to undertake the detector-specific computing. The algorithm principles will be explained and hardware designs are described in the paper. The current progress reveals the feasibility to implement these algorithms on FPGAs. Also experimental results demonstrate the performance speedup when compared to alternative software solutions, as well as the potential capability of high-speed parallel/pipelined processing in Data Acquisition and Trigger systems.
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| 14. |
- Lu, Zhonghai, et al.
(författare)
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Layered switching for networks on chip
- 2007
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Ingår i: 2007 44th ACM/IEEE Design Automation Conference, Vols 1 And 2. - 9781595937711 ; , s. 122-127
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Konferensbidrag (refereegranskat)abstract
- We present and evaluate a novel switching mechanism called layered switching. Conceptually, the layered switching implements wormhole on top of virtual cut-through switching. To show the feasibility of layered switching, as well as to confirm its advantages, we conducted an RTL implementation study based on a canonical wormhole architecture. Synthesis results show that our strategy suggests negligible degradation in hardware speed (1%) and area overhead (7%). Simulation results demonstrate that it achieves higher throughput than wormhole alone while significantly reducing the buffer space required at network nodes when compared with virtual cut-through.
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| 15. |
- Wang, Qiang, et al.
(författare)
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Hardware/Software Co-design of an ATCA-based Computation Platform for Data Acquisition and Triggering
- 2009
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Ingår i: 16th IEEE NPSS Real Time Conference. - 9781424457960 ; , s. 485-489
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Konferensbidrag (refereegranskat)abstract
- An ATCA-based computation platform for data acquisition and trigger(TDAQ) applications has been developed for multiple future projects such its PANDA. HADES, and BESIII. Each Compute Node (CN) appears as one (if the fourteen Field Replaceable Units (FRU) in an ATCA shelf, which in total features a high performance of 1890 Clips inter-FPGA on-board channels, 1456 Gbps inter-board backplane connections, 728 Gbps full-duplex optical links, 70 Gbps Ethernet. 140 GBytes DDR2 SDRAM. and all computing resources of 70 Xilinx Virtex-4 FX60 FPGAs. Corresponding to (the system architecture, a hardware/software co-design approach is proposed to ease and accelerate the development for different experiments. In the uniform system design. application-specific computation is to be implemented as customized hardware co-processors, while the embedded PowerPC processor takes charge of flexible slow controls and transmission protocol processing.
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