| 1. |
- Andreani, Pietro, et al.
(author)
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A 2.3 GHz LC-Tank CMOS VCO with Optimal Phase Noise Performance
- 2006
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In: Digest of Technical Papers - IEEE International Solid-State Circuits Conference. - 1424400791 - 9781424400799 ; , s. 691-700
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Conference paper (other academic/artistic)abstract
- The phase-noise theory and design of a differential CMOS LC-tank VCO with double switch pair is presented. A formula for the minimum achievable phase noise in the 1/f2 region is derived. The 2.15 to 2.35GHz 0.3μm CMOS VCO has a phase noise of -143.9dBc/Hz at 3MHz offset and draws 4mA from a 2.5V supply.
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| 2. |
- Andreasson, Jens, et al.
(author)
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Remote system for patient monitoring using bluetooth
- 2002
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In: Proceedings of IEEE SensorsVolume 1, Issue 1, 2002. - 0780374541 ; , s. 304-307
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Conference paper (other academic/artistic)abstract
- The aim of this study is to design and develop a low-power wireless A/D-converter that should be easy to integrate with other technologies or infrastructures at a low cost. This transmitting unit should be able to replace many of the signal wires between biomedical sensors connecting the patient and the sampling unit or supervision equipment. The model of today is an embedded hardware solution with two processors (FPGA and Bluetooth). A twelve bit ADC with a 1 kHz-sampling rate then converts an analogue signal that simulates an ECG-signal with typical frequencies. The communication between the ADC and Bluetooth™ is serial and controlled by the FPGA. The remote PC runs a simple software that controls the Bluetooth™ and processes the received data. The results indicate that it is possible to continuously transmit an ECG-signal without loosing data.
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| 3. |
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| 4. |
- Fard, Ali, et al.
(author)
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A Low-Phase-Noise Wide-Band CMOS Quadrature VCO for Multi-Standard RF Front-Ends
- 2005
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In: Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium. - 0780389832 ; , s. 539-542
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Conference paper (other academic/artistic)abstract
- A low phase noise CMOS LC quadrature VCO (QVCO) with a wide frequency range of 3.6-5.6 GHz, designed in a standard 0.18 μm process for multi-standard front-ends, is presented. A significant advantage of the topology is the larger oscillation amplitude when compared to other conventional QVCO structures. The QVCO is compared to a double cross-coupled LC-tank differential oscillator, both in theory and experiments, for evaluation of its phase noise, providing a good insight into its performance. The measured data displays up to 2 dBc/Hz lower phase noise in the 1/f2 region for the QVCO, when consuming twice the current of the differential VCO, based on an identical LC-tank. Experimental results on the QVCO show a phase noise level of -127.5 dBc/Hz at 3 MHz offset from a 5.6 GHz carrier while dissipating 8 mA of current, resulting in a figure of merit of 181.3 dBc/Hz.
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| 5. |
- Fard, Ali, et al.
(author)
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A Low Power Wide-Band CMOS VCO for Multi-Standard Radios
- 2004
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In: Proceedings - 2004 IEEE Radio and Wireless Conference, RAWCON. - 0780384512 ; , s. 79-82
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Conference paper (other academic/artistic)abstract
- This paper presents a single monolithic wide band VCO for multi-standard radios. Analysis on a differential switched capacitor circuit is performed. Its impact on phase noise and power dissipation is especially addressed. The analysis is demonstrated and verified in a fully integrated CMOS VCO that consumes 2.7 mA from a 1.8 V supply and operates with a wide frequency band from 3.5 - 5.3 GHz. The measured phase noise is less than -110 dBc/Hz at 1 MHz offset within the entire tuning range.
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| 6. |
- Fard, Ali, et al.
(author)
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A novel 18 GHz 1.3 mW CMOS frequency divider with high input sensitivity
- 2005
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In: ISSCS 2005: International Symposium on Signals, Circuits and Systems - Proceedings. - 9780780390294 ; , s. 409-412
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Conference paper (other academic/artistic)abstract
- A novel CMOS high speed divide-by-two circuit with very low power consumption is proposed in this paper. The circuit features very low input capacitance and a wide locking range of 1.5-18 GHz with a power consumption of less than 13 mW at 1.8 V. The input sensitivity of the stage is improved significantly when compared to conventional dynamic loaded high frequency dividers. The concept and design issue of the circuit is presented together with a performance comparison to existing topologies. The idea is demonstrated and verified in a standard 0.18 μm CMOS process through realistic simulations originating from a complete layout using moderately extracted parasitics.
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| 7. |
- Fard, Ali, et al.
(author)
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A Reconfigurable CMOS VCO with and Automatic Amplitude Controller for Multi-Band RF Front-Ends
- 2005
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In: Proceedings of the 2005 European Conference on Circuit Theory and Design. - 9780780390669 ; , s. 95-98
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Conference paper (other academic/artistic)abstract
- A fully integrated reconfigurable 3.6-6.0 GHz 0.18μm CMOS VCO with an automatic amplitude controller (AAC) for multi-standard front-ends is proposed. Due to the wide tuning range, utilizing mixed tuning technique, large amplitude variations over the band are observed. Thus a novel low noise AAC is implemented to stabilize the amplitude regardless of operation frequency. Measurements are performed both with and without the AAC loop active, showing that the AAC loops noise contributions are very small. The circuit displays phase noise levels of-124 dBc/Hz or less at 3 MHz offset within the entire frequency band while consuming 7.7-12.2 mW of power. The relative amplitude variation over the frequency band are 100 mV.
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| 8. |
- Fard, Ali, 1978-
(author)
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Analysis and Design of Low-Phase-Noise Integrated Voltage-Controlled Oscillators for Wide-Band RF Front-Ends
- 2006
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Doctoral thesis (other academic/artistic)abstract
- The explosive development of wireless communication services creates a demand for more flexible and cost-effective communication systems that offer higher data rates. The obvious trend towards small-size and ultra low power systems, in combination with the ever increasing number of applications integrated in a single portable device, tightens the design constraints at hardware and software level. The integration of current mobile systems with the third generation systems exemplifies and emphasizes the need of monolithic multi-band transceivers. A long term goal is a software defined radio, where several communication standards and applications are embedded and reconfigured by software. This motivates the need for highly flexible and reconfigurable analog radio frequency (RF) circuits that can be fully integrated in standard low-cost complementary metal-oxide-semiconductor (CMOS) technologies.In this thesis, the Voltage-Controlled Oscillator (VCO), one of the main challenging RF circuits within a transceiver, is investigated for today’s and future communication systems. The contributions from this work may be divided into two parts. The first part exploits the possibility and design related issues of wide-band reconfigurable integrated VCOs in CMOS technologies. Aspects such as frequency tuning, power dissipation and phase noise performance are studied and design oriented techniques for wide-band circuit solutions are proposed. For demonstration of these investigations several fully functional wide-band multi-GHz VCOs are implemented and characterized in a 0.18µm CMOS technology.The second part of the thesis concerns theoretical analysis of phase noise in VCOs. Due to the complex process of conversion from component noise to phase noise, computer aided methods or advanced circuit simulators are usually used for evaluation and prediction of phase noise. As a consequence, the fundamental properties of different noise sources and their impact on phase noise in commonly adopted VCO topologies have so far not been completely described. This in turn makes the optimization process of integrated VCOs a very complex task. To aid the design and to provide a deeper understanding of the phase noise mechanism, a new approach based on a linear time-variant model is proposed in this work. The theory allows for derivation of analytic expressions for phase noise, thereby, providing excellent insight on how to minimize and optimize phase noise in oscillators as a function of circuit related parameters. Moreover, it enables a fair performance comparison of different oscillator topologies in order to ascertain which structure is most suitable depending on the application of interest. The proposed method is verified with very good agreement against both advanced circuit simulations and measurements in CMOS and bipolar technologies. As a final contribution, using the knowledge gained from the theoretical analysis, a fully integrated 0.35µm CMOS VCO with superior phase noise performance and power dissipation is demonstrated.
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| 9. |
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| 10. |
- Fard, Ali, et al.
(author)
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Design of a dual-band 5/2.4 GHZ CMOS VCO for 802.11 A/B/G WLAN transceivers
- 2004
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In: IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, Volume 1, 2004. - 0780386604 ; , s. 429-432
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Conference paper (other academic/artistic)abstract
- A dual-band CMOS VCO with a divide-by-two circuit, operating between 4.7-6.2/2.35-3.1 GHz is demonstrated in a 0.35mum process. The VCO phase noise is reduced by matching the transconductance and impedance of the active devices. By using a divide-by-two stage quadrature signals for the 802.11 b/g standards are obtained. The VCO is optimized for low phase noise and small amplitude variations across the tuning range. The phase noise levels are less than -116.5 and -126 dBc/Hz at 1 MHz offset in the upper and lower frequency band respectively.
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