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Mapping Optimisatio...
Mapping Optimisation for Scalable multi-core ARchiTecture : The MOSART approach
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Candaele, Bernard (author)
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Aguirre, Sylvain (author)
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Sarlotte, Michel (author)
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Anagnostopoulos, Iraklis (author)
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Xydis, Sotirios (author)
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Bartzas, Alexandros (author)
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Bekiaris, Dimitris (author)
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Soudris, Dimitrios (author)
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- Lu, Zhonghai (author)
- KTH,Elektroniksystem
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- Chen, Xiaowen (author)
- KTH,Elektronik- och datorsystem, ECS
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- Chabloz, Jean-Michel (author)
- KTH,Elektronik- och datorsystem, ECS
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- Hemani, Ahmed (author)
- KTH,Elektronik- och datorsystem, ECS
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- Jantsch, Axel (author)
- KTH,Elektronik- och datorsystem, ECS
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Vanmeerbeeck, Geert (author)
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Kreku, Jari (author)
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Tiensyrja, Kari (author)
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Ieromnimon, Fragkiskos (author)
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Kritharidis, Dimitrios (author)
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Wiefrink, Andreas (author)
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Vanthournout, Bart (author)
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Martin, Philippe (author)
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(creator_code:org_t)
- 2010
- 2010
- English.
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In: Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010. - 9780769540764 ; , s. 518-523
- Related links:
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https://urn.kb.se/re...
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https://doi.org/10.1...
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Abstract
Subject headings
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- The project will address two main challenges of prevailing architectures: 1) The global Interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption; 2) The difficulties in programming heterogeneous, multi-core platforms, in particular in dynamically managing data structures in distributed memory. MOSART aims to overcome these through a multi-core architecture with distributed memory organisation, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimised and customised together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: A) Providing platform support for management of abstract data structures Including middleware services and a run-time data manager for NoC based communication infrastructure; 2) Developing tool support for parallelizing and mapping applications on the multi-core target platform and customizing the processing cores for the application.
Subject headings
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)
Keyword
- Data structures
- Middleware
- VLSI circuits
Publication and Content Type
- ref (subject category)
- kon (subject category)
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- By the author/editor
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Candaele, Bernar ...
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Aguirre, Sylvain
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Sarlotte, Michel
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Anagnostopoulos, ...
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Xydis, Sotirios
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Bartzas, Alexand ...
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show more...
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Bekiaris, Dimitr ...
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Soudris, Dimitri ...
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Lu, Zhonghai
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Chen, Xiaowen
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Chabloz, Jean-Mi ...
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Hemani, Ahmed
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Jantsch, Axel
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Vanmeerbeeck, Ge ...
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Kreku, Jari
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Tiensyrja, Kari
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Ieromnimon, Frag ...
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Kritharidis, Dim ...
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Wiefrink, Andrea ...
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Vanthournout, Ba ...
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Martin, Philippe
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- About the subject
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- ENGINEERING AND TECHNOLOGY
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ENGINEERING AND ...
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and Electrical Engin ...
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Proceedings - IE ...
- By the university
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Royal Institute of Technology