| 1. |
- Balestra, F., et al.
(author)
-
NANOSIL network of excellence-silicon-based nanostructures and nanodevices for long-term nanoelectronics applications
- 2008
-
In: Materials Science in Semiconductor Processing. - : Elsevier BV. - 1369-8001 .- 1873-4081. ; 11:5-6, s. 148-159
-
Journal article (peer-reviewed)abstract
- NANOSIL Network of Excellence [NANOSIL NoE web site < www.nanosil-noe.eu >], funded by the European Commission in the 7th Framework Programme (ICT-FP7, no 216171), aims at European scale integration of the excellent European research laboratories and their capabilities in order to strengthen scientific and technological excellence in the field of nanoelectronic materials and devices for terascale integrated circuits (ICs), and to disseminating the results in a wide scientific and industrial community. NANOSIL is exploring and assessing the science and technological aspects of nanodevices and operational regimes relevant to the n+4 technology node and beyond. It encompasses projects on nanoscale CMOS and beyond-CMOS. Innovative concepts, technologies and device architectures are proposed-with fabrication down to the finest features, and utilising a wide spectrum of advanced deposition and processing capabilities, extensive characterization and very rigorous device modeling. This work is carried out through a network of joint processing, characterization and modeling platforms. This critical interaction strengthens European integration in nanoelectronics and will speed up technological innovation for the nanoelectronics of the next two to three decades.
|
|
| 2. |
- Fu, Ying, 1964, et al.
(author)
-
Emission rates for electron tunneling from InAs quantum dots to GaAs substrate
- 2004
-
In: Journal of Applied Physics. - : AIP Publishing. - 0021-8979 .- 1089-7550. ; 96:11, s. 6477-6481
-
Journal article (peer-reviewed)abstract
- Tunneling emission rates of electrons from InAs quantum dots (QD) in a GaAs matrix depletion region have been calculated for application in the analysis of experimental data from deep-level transient spectroscopy (DLTS). The hybridization among metastable states localized in the InAs QD and continuum states in the GaAs substrate in the DLTS measurement is evaluated from the local densities of states. Two physical quantities have been calculated, the broadening of the metastable state localized in the InAs QD, i.e., the charge-transfer rates from the quantum dot to the substrate, and the corresponding hybridization coefficients. The metastable state is broadened significantly only when the bias is large enough, whereas the hybridization coefficients increase almost linearly with the bias. The effects of the direct Coulomb interactions and exchange energies among electrons initially confined in the QD have been included and found to be very significant. Increasing the number of electrons initially confined in the QD from 1 to 4, the charge-transfer rates increase by a factor of 1.8.
|
|
| 3. |
- Gottlob, H. D. B., et al.
(author)
-
Gd silicate : A high-k dielectric compatible with high temperature annealing
- 2009
-
In: Journal of Vacuum Science & Technology B. - : American Vacuum Society. - 1071-1023 .- 1520-8567 .- 2166-2754 .- 2166-2746. ; 27:1, s. 249-252
-
Journal article (peer-reviewed)abstract
- The authors report on the investigation of amorphous Gd-based silicates as high-k dielectrics. Two different stacks of amorphous gadolinium oxide (Gd(2)O(3)) and silicon oxide (SiO(2)) on silicon substrates are compared after annealing at temperatures up to 1000 degrees C. Subsequently formed metal oxide semiconductor capacitors show a significant reduction in the capacitance equivalent thicknesses after annealing. Transmission electron microscopy, medium energy ion scattering, and x-ray diffraction analysis reveal distinct structural changes such as consumption of the SiO(2) layer and formation of amorphous Gd silicate. The controlled formation of Gd silicates in this work indicates a route toward high-k dielectrics compatible with conventional, gate first complementary metal-oxide semiconductor integration schemes.
|
|
| 4. |
- Gottlob, H. D. B., et al.
(author)
-
Scaling potential and MOSFET integration of thermally stable Gd silicate dielectrics
- 2009
-
In: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 86:7-9, s. 1642-1645
-
Journal article (peer-reviewed)abstract
- We investigate the potential of gadolinium silicate (GdSiO) as a thermally stable high-k gate dielectric in a gate first integration scheme. There silicon diffuses into gadolinium oxide (Gd2O3) from a silicon oxide (SiO2) interlayer specifically prepared for this purpose. We report on the scaling potential based on detailed material analysis. Gate leakage current densities and EOT values are compatible with an ITRS requirement for low stand by power (LSTP). The applicability of this GdSiO process is demonstrated by fully functional silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs). (C) 2009 Elsevier B.V. All rights reserved.
|
|
| 5. |
- Lu, Y., et al.
(author)
-
Leakage current effects on C-V plots of high-k metal-oxide-semiconductor capacitors
- 2009
-
In: Journal of Vacuum Science & Technology B. - : American Vacuum Society. - 1071-1023 .- 1520-8567 .- 2166-2754 .- 2166-2746. ; 27:1, s. 352-355
-
Journal article (peer-reviewed)abstract
- With the employment of ultrathin, high dielectric constant gate materials in advanced semiconductor technology, the conventional capacitance-voltage measurement technique exhibits a series of anomalies. In particular, a nonsaturating increase in the accumulation capacitance with reducing measurement frequency is frequently observed, which has not been adequately explained to our knowledge. In this article, the authors provide an explanation for this anomaly and hence set a criterion for the lower bound on measurement frequency. We then present a model which allows the easy extraction of the required parameters and apply it to an experimental set of data.
|
|
| 6. |
- Raeissi, Bahman, 1979, et al.
(author)
-
High-k-oxide/silicon interfaces characterized by capacitance frequency spectroscopy
- 2007
-
In: ESSDERC 2007. - 9781424411238 ; , s. 283-286
-
Conference paper (peer-reviewed)abstract
- Electron capture into insulator/silicon interface states is investigated for high-k dielectrics of Gd(2)O(3) prepared by MBE and ALD, and for HfO(2) prepared by reactive sputtering, by measuring the frequency dependence of MOS capacitance. The capture cross sections are found to be thermally activated and to increase steeply with the energy depth of the interface electron states. The methodology adopted is considered useful for increasing the understanding of high-k-oxide/silicon interfaces.
|
|
| 7. |
- Raeissi, Bahman, 1979, et al.
(author)
-
High-k-oxide/silicon interfaces characterized by capacitance frequency spectroscopy
- 2008
-
In: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 52:9, s. 1274-1279
-
Journal article (peer-reviewed)abstract
- Electron capture into insulator/silicon interface states is investigated for high-k dielectrics of Gd2O3 preparedby molecular beam epitaxy (MBE) and atomic layer deposition (ALD), and for HfO2 prepared byreactive sputtering, by measuring the frequency dependence of Metal Oxide Semiconductor (MOS) capacitance.The capture cross sections are found to be thermally activated and to increase steeply with theenergy depth of the interface electron states. The methodology adopted is considered useful for increasingthe understanding of high-k-oxide/silicon interfaces.
|
|
