| 61. |
- Forsell, Martti, et al.
(författare)
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Networks on Chip : Approaches and Challenges
- 2004
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Ingår i: Research and Development Activities in Telecommunication Systems. - : VTT Electronics. ; , s. 55-61
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Bokkapitel (refereegranskat)
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| 62. |
- Grange, Matt, et al.
(författare)
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Modeling the Computational Efficiency of 2-D and 3-D Silicon Processors for Early-Chip Planning
- 2011
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Ingår i: 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). - 9781457713989 - 9781457713996 ; , s. 310-317
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Konferensbidrag (refereegranskat)abstract
- Hierarchical models from physical to system-level are proposed for architectural exploration of high-performance silicon systems to quantify the performance and cost trade offs for 2-D and 3-D IC implementations. We show that 3-D systems can reduce interconnect delay and energy by up to an order of magnitude over 2-D, with an increase of 20-30% in performance-per-watt for every doubling of stack height. Contrary to previous analysis, the improved energy efficiency is achievable at a favorable cost. The models are packaged as a standalone tool and can provide fast estimation of coarse-grain performance and cost limitations for a variety of processing systems to be used at the early chip-planning phase of the design cycle.
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| 63. |
- Grange, Matt, et al.
(författare)
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Modeling the Efficiency of Stacked Silicon Systems : Computational, Thermal and Electrical Performance
- 2011
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Konferensbidrag (refereegranskat)abstract
- Technological advances in processor design have typically reliedon scaling feature size and frequency. Recently however, many new design choiceshave emerged partly due to the slowing of scaling:– Many-core architectures arebeginning to replace single-core ICs to circumvent 2-D bottlenecks, The number ofI/Os are on the rise, so the cost of off-chip transactions is becoming heftier. Moreover,3-D Integration may provide further performance benefits without investment in lowertechnology nodes. Understanding these trade-offs can provide guidelines to optimizethe architecture of future systems under performance, thermal and cost constraints.We have constructed a model and tool that assesses computational efficiency underthese criteria.
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| 64. |
- Grange, Matt, et al.
(författare)
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Optimal Network Architectures for Minimizing Average Distance in k-ary n-dimensional Mesh Networks
- 2011
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Ingår i: NOCS 2011: The 5th ACM/IEEE International Symposium on Networks-on-Chip. - New York, NY, USA : ACM Digital Library. ; , s. 57-64
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Konferensbidrag (refereegranskat)abstract
- A general expression for the average distance for meshes of any dimension and radix, including unequal radices in different dimensions, valid for any traffic pattern under zero-load condition is formulated rigorously to allow its calculation without network-level simulations. The average distance expression is solved analytically for uniform random traffic and for a set of local random traffic patterns. Hot spot traffic patterns are also considered and the formula is empirically validated by cycle true simulations for uniform random, local, and hot spot traffic. Moreover, a methodology to attain closed-form solutions for other traffic patterns is detailed. Furthermore, the model is applied to guide design decisions. Specifically, we show that the model can predict the optimal 3-D topology for uniform and local traffic patterns. It can also predict the optimal placement of hot spots in the network. The fidelity of the approach in suggesting the correct design choices even for loaded and congested networks is surprising. For those cases we studied empirically it is 100%.
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| 65. |
- Grange, Matt, et al.
(författare)
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Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh
- 2009
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Ingår i: 2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION. - San Francisco : IEEE conference proceedings. - 9781424445110 ; , s. 345-351
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Konferensbidrag (refereegranskat)abstract
- The physical performance of a 3-Dimensional Network-on-Chip (NoC) mesh architecture employing through silicon vias (TSV) for vertical connectivity is investigated with a cycle-accurate RTL simulator. The physical latency and area impact of TSVs, switches, and the on-chip interconnect is evaluated to extract the maximum signaling speeds through the switches, horizontal and vertical network links. The relatively low parasitics of TSVs compared to the on-chip 2-D interconnect allow for higher signaling speeds between chip layers. The system-level impact on overall network performance as a result of clocking vertical packets at a higher rate through the TSV interconnect is simulated and reported.
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| 66. |
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| 67. |
- Grecu, Cristian, et al.
(författare)
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Towards open network-on-chip benchmarks
- 2007
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Ingår i: NOCS 2007. ; , s. 205-212
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Konferensbidrag (refereegranskat)abstract
- Measuring and comparing performance, cost, and other features of advanced communication architectures for complex multi core/multiprocessor systems on chip is a significant challenge which has hardly been addressed so far. This document outlines the top-level view on a system of benchmarks for Networks on Chip (NoC), which intends to cover a wide spectrum of NoC design aspects, from application modeling to performance evaluation and post-manufacturing test and reliability. For performance benchmarking, requirements and features are described for application programs, synthetic micro-benchmarks, and abstract benchmark applications. Then, it proposes ways to measure and benchmark reliability, fault tolerance and testability of the on-chip communication fabric. This paper introduces the main concepts and ideas for benchmarking NoCs in a systematic and comparable way. It will be followed up by a report that will define a benchmark framework and the syntax of interfaces for benchmark programs that will allow the community to build-up a benchmark suite.
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| 68. |
- Grimm, Christoph, et al.
(författare)
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C-Based Design of Embedded Systems - Editorial
- 2008
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Ingår i: EURASIP Journal on Embedded Systems. - : Springer Science and Business Media LLC. - 1687-3955 .- 1687-3963. ; :1, s. 243890-
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Tidskriftsartikel (övrigt vetenskapligt/konstnärligt)
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| 69. |
- Guang, Liang, et al.
(författare)
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Adaptive Power Management for the On-Chip Communication Network
- 2006
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Ingår i: DSD 2006. - 0769526098 ; , s. 649-656
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Konferensbidrag (refereegranskat)abstract
- An on-chip communication network is most power efficient when it operates just below the saturation point. For any given traffic load the network can be operated in this region by adjusting frequency and voltage. For a deflective routing network we propose the design of a central controller for dynamic frequency and voltage scaling. Given history information including the load and frequency in the network, the controller adjusts the frequency and voltage such that the network operates just below the saturation point. We provide control mechanisms for continuous and discrete frequency ranges. With a discrete frequency range and taking into account voltage switching delays, we evaluate the control mechanism under stochastic, smoothly varying and very bursty traffic. Experiments demonstrate that adaptive control is very effective in minimizing power consumption at reasonable performance. Compared with a fixed high frequency network, the adaptively controlled network is significantly more power efficient. We compare it to fixed frequency networks, which are either too slow exhibiting unbounded delays, or are dimensioned for the worst case with very high frequency and are very power hungry.
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| 70. |
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