| 31. |
- Spaanenburg, Henk A.E., et al.
(författare)
-
The need for large local FPGA-accessible memories
- 2006
-
Ingår i: Proceedings ISCAS. - 0780393902 ; , s. 1957-1960
-
Konferensbidrag (refereegranskat)abstract
- Advanced Principles Group (APG) has developed a Reconfigurable Computing Board (RCB) based on the Xilinx Virtex-II Pro FPGA family, potentially capable of 1.5 - 2.0 TeraOps of compute power, 100 Gbps I/O on front panel, 4 Gbps I/O on backplane, as well as containing more than 4 GBytes of on-board memory. Computationally complex applications such as Software-Defined Radio, Synthetic Aperture Radar, Hyper-Spectral Imaging and Cellular Neural Networks drive similar wide bandwidths and therefore require super-computing I/O and signal processing densities far exceeding the capabilities of current and future microprocessor-based system technology. We illustrate how such applications benefit from the large amount of local FPGA-accessible memory (4+ GBytes) provided on the RCB.
|
|
| 32. |
- Spaanenburg, Lambert, et al.
(författare)
-
3D-design exploration of CNN algorithms
- 2011
-
Ingår i: VLSI Circuits and Systems V. - : SPIE. - 0277-786X .- 1996-756X. ; 8067
-
Konferensbidrag (refereegranskat)abstract
- Multi-dimensional algorithms are hard to implement on classical platforms. Pipelining may exploit instruction-level parallelism, but not in the presence of simultaneous data; threads optimize only within the given restrictions. Tiled architectures do add a dimension to the solution space. With locally a large register store, data parallelism is handled, but only to a dimension. 3-D technologies are meant to add a dimension in the realization. Applied on the device level, it makes each computational node smaller. The interconnections become shorter and hence the network will be condensed. Such advantages will be easily lost at higher implementation levels unless 3-D technologies as multi-cores or chip stacking are also introduced. 3-D technologies scale in space, where (partial) reconfiguration scales in time. The optimal selection over the various implementation levels is algorithm dependent. The paper discusses such principles while applied on the scaling of cellular neural networks (CNN). It illustrates how stacking of reconfigurable chips supports many algorithmic requirements in a defect-insensitive manner. Further the paper explores the potential of chip stacking for multi-modal implementations in a reconfigurable approach to heterogeneous architectures for algorithm domains.
|
|
| 33. |
- Spaanenburg, Lambert, et al.
(författare)
-
Artificial life goes 'in silico'
- 2005
-
Ingår i: Proceedings of the 2005 IEEE International Conference on Computational Intelligence for Measurement Systems and Applications. - 0780390253 ; , s. 267-272, s. 154-165
-
Konferensbidrag (refereegranskat)abstract
- The paper reviews a number of cellular neural network implementations on a field-programmable gate-array. It illustrates experimentally, how these implementations can be used to measure from images or to create dynamic, autonomous processes that facilitate measurements within topographic maps. Applications range from image understanding to robot navigation
|
|
| 34. |
- Spaanenburg, Lambert, et al.
(författare)
-
Behavior Modeling by Neural Networks
- 2009
-
Ingår i: Artificial Neural Networks - ICANN 2009, Pt I (Lecture Notes in Computer Science). - Berlin, Heidelberg : Springer Berlin Heidelberg. - 1611-3349 .- 0302-9743. - 9783642042737 ; 5768, s. 439-448
-
Konferensbidrag (refereegranskat)abstract
- Modeling of human and animal behavior is of interest for a number of diagnostic purposes. Convolutional neural networks offer a constructive approach allowing learning on a limited number of examples. Chaotic tendencies make that learning is not always successful. The paper looks into a number of applications to find the reason for this anomaly and identifies the need for behavioral references to provide determinism in the diagnostic model.
|
|
| 35. |
- Spaanenburg, Lambert, et al.
(författare)
-
Design method for Unconventional Computing
- 2006
-
Ingår i: Proceedings 10th IEEE Workshop on CNNA and their Applications. - 1424406404 ; , s. 334-339
-
Konferensbidrag (refereegranskat)abstract
- Network-on-Chip concepts allow moving away from the classical, centralized computer. The meaningful collaboration of computing units over a well-behaved network creates the infinite state space that underlies the Turing computer concept. The combinatorial state explosion that results from a Network-on-Chip will easily prove more valuable than the mere technological progress in memory storage, when the network nodes become small enough. Embedded Super-Computing has this unconventional goal. This paper introduces a design method for such computing concepts. It discusses how a software simulation is gradually migrated into a Network-on-Chip implementation. The approach is illustrated by the development of a Cellular Neural Network as a typical example of a well-behaved network on small, embedded nodes.
|
|
| 36. |
- Spaanenburg, Lambert
(författare)
-
Early detection of abnormal emergent behaviour
- 2007
-
Ingår i: Proceedings European Signal Processing Conference. ; , s. 1741-1744
-
Konferensbidrag (refereegranskat)abstract
- Emergent behaviour has become a plague of automation systems based on communication networks. Centralized monitoring of the network comes generally to late to sup-press unwanted behaviour. It is required to mark the ten-dency towards state changes in a decentralized manner. The paper discusses the role of local awareness by inspection of the model learning behaviour of feed-forward networks. The correlated movement of weight changes over time provides a clear indication of such profound changes, as demonstrated by some initial experience in industrial automation.
|
|
| 37. |
- Spaanenburg, Lambert, et al.
(författare)
-
Embedded sensory systems based on topographic maps
- 2003
-
Ingår i: Proceedings Progress 03. - 9073461375 ; , s. 232-237
-
Konferensbidrag (refereegranskat)abstract
- Image processing is one of the popular applications of Cellular Neural Networks. Macro enriched field-programmable gate-arrays can be used to realize such systems on silicon. The paper discusses a pipelined implementation that supports the handling of gray-level images at 180 to 240 Mpixels per second by exploiting the Virtex-II macros to spatially unroll the local feedback.
|
|
| 38. |
- Spaanenburg, Lambert
(författare)
-
Ensuring Safety in Distributed Networks
- 2010
-
Ingår i: 49th IEEE Conference on Decision and Control. - 9781424477449 ; , s. 6815-6820
-
Konferensbidrag (refereegranskat)abstract
- Large-scale distributed networks are not easy to control centrally. Local set-point variations will likely create flooding alarm fluctuations. However, local control can cause emergence of unwanted network behavior. The paper overviews the problems with model-based control in sensory networks, such as currently rolled out for the Electric Grid, and shows how networked intelligence can bridge between central and distributed control.
|
|
| 39. |
- Spaanenburg, Lambert, et al.
(författare)
-
Natural learning of neural networks by reconfiguration
- 2003
-
Ingår i: SPIE Proceedings on Bioengineered and Bioinspired Systems. - : SPIE. - 1996-756X .- 0277-786X. ; 5119, s. 273-284
-
Konferensbidrag (refereegranskat)abstract
- The communicational and computational demands of neural networks are hard to satisfy in a digital technology. Temporal computing solves this problem by iteration, but leaves a slow network. Spatial computing was no option until the coming of modern FPGA devices. The letter shows how a small feed-forward neural module can be configured on the limited logic blocks between RAM and multiplier macro’s. It is then described how by spatial unrolling or by reconfiguration a large modular ANN can be built from such modules.
|
|
| 40. |
- Spaanenburg, Lambert, et al.
(författare)
-
Self-similar module for FP/LNS arithmetic in high-performance FPGA systems
- 2005
-
Ingår i: Proceedings of SPIE - The International Society for Optical Engineering. - : SPIE. - 0277-786X .- 1996-756X. ; 5837 PART II, s. 880-887
-
Konferensbidrag (refereegranskat)abstract
- The scientific community has gratefully embraced floating-point arithmetic to escape the close attention for accuracy and precision required in fixed-point computational styles. Though its deficiencies are well known, the role of the floating-point system as standard has kept other number representation systems from coming into practice. The paper discusses the relation between fixed and floating-point numbers from a pragmatic point of view that allows to mix both systems to optimize FPGA-based hardware accelerators. The method is developed for the Mitrion "processor on demand" technology, where a computationally intensive algorithm is transformed into a dedicated. The large gap in cycle time between fixed and floating-point operations and between direct and reverse operations makes the on-chip control for the fine-grain pipelines of parallel logic very complicated. Having alternative hardware realizations available can alleviate this. The paper uses a conjunctive notation, also known as DIGILOG, to introduce a flexible means in creating configurable arithmetic of arbitrary order using a single module type. This allows the Mitrion hardware compiler to match the hardware closer to the demands of the specific algorithm. Typical applications are in molecular simulation and real-time image analysis.
|
|
