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| 2. |
- Ellervee, Peeter, et al.
(författare)
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Exploring ASIC Design Space at System Level with a Neural Network Estimator
- 1994
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Ingår i: Proc. of IEEE ASIC-conference, 1994.
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Konferensbidrag (refereegranskat)abstract
- Estimators are critical tools in doing architectural level exploration of the design space. We present a novel approach to estimation based on the multilayer perceptron which builds the estimation function during the learning process and thus allows to describe arbitrary complex functions. We also describe how the control data flow graph is encoded for the neural network input and we present results of the first experiments made with realistic design examples.
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| 3. |
- Isoaho, Jouni, et al.
(författare)
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High level synthesis in DSP ASIC optimization
- 1994
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Ingår i: Proc. of 7th IEEE ASIC Conference and Exhibit. ; , s. 75-78
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Konferensbidrag (refereegranskat)abstract
- In this paper Digital Signal Processing (DSP) system optimization with High Level Synthesis (HLS) environment is presented. To optimize a behavioural VHDL description, commercial SYNT and Synopsys synthesis tools are utilized. The optimization results are improved with a simple rule based preallocator. The coefficient optimization is done in Matlab to provide an efficient implementation of power-of-two and multiply-accumulate based FIR filters. The optimization results are presented using practical filter examples
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| 4. |
- Isoaho, Jouni, et al.
(författare)
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HLS based DSP optimization with ASIC RTL libraries
- 1994
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Ingår i: ; , s. 218-225
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Konferensbidrag (refereegranskat)abstract
- In this paper we show how the High Level Synthesis (HLS) tool can efficiently be used for DSP ASIC development. The performance of general HLS tool is improved with simple transformations and code optimizations, and a direct mapping to technology optimized parameterizable ASIC Register Transfer Level (RTL) library. The library mapping contains three phases: a structure recognition, an architecture selection and a parameter optimization. As an optimization framework SYNT, Synopsys and Matlab design environments are integrated. Lsi10k and Xilinx 4000 series are used as target technologies to demonstrate the performance of the approach
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| 5. |
- Jantsch, Axel, et al.
(författare)
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A Case Study on Hardware/Software Partitioning
- 1994
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Ingår i: Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines. - : IEEE conference proceedings. - 0818654902 ; , s. 111-118
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Konferensbidrag (refereegranskat)abstract
- We present an analysis of a fully automatic method to accelerate standard software in C or C++ by use of field programmable gate arrays. Traditional compiler techniques are applied to the hardware/software partitioning problem and a compiler is linked to state of the art hardware synthesis tools. Time critical regions are identified by means of profiling and are automatically implemented in user programmable logic with high level and logic synthesis design tools. The underlying architecture is an add-on board with user programmable logic connected to a Spare based workstation via the system bus. We present an analysis and case study of this method. Eight programs are used as test cases and the data collected by applying this method to programs is used to discuss potentials and limitations of this and similar methods. We discuss architectural parameters, programming language properties, and analysis techniques.
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