| 1. |
- Candaele, Bernard, et al.
(författare)
-
Mapping Optimisation for Scalable multi-core ARchiTecture : The MOSART approach
- 2010
-
Ingår i: Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010. - 9780769540764 ; , s. 518-523
-
Konferensbidrag (refereegranskat)abstract
- The project will address two main challenges of prevailing architectures: 1) The global Interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption; 2) The difficulties in programming heterogeneous, multi-core platforms, in particular in dynamically managing data structures in distributed memory. MOSART aims to overcome these through a multi-core architecture with distributed memory organisation, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimised and customised together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: A) Providing platform support for management of abstract data structures Including middleware services and a run-time data manager for NoC based communication infrastructure; 2) Developing tool support for parallelizing and mapping applications on the multi-core target platform and customizing the processing cores for the application.
|
|
| 2. |
- Candaele, Bernard, et al.
(författare)
-
The MOSART Mapping Optimization for multi-core Architectures
- 2011
-
Ingår i: VLSI 2010 Annual Symposium. - Dordrecht : Springer Publishing Company. ; , s. 181-195
-
Konferensbidrag (refereegranskat)abstract
- MOSART project addresses two main challenges of prevailing architectures: (i) Theglobal interconnect and memory bottleneck due to a single, globally shared memorywith high access times and power consumption; (ii) The difficulties in programmingheterogeneous, multi-core platforms MOSART aims to overcome these through amulti-core architecture with distributed memory organization, a Network-on-Chip(NoC) communication backbone and configurable processing cores that are scaled,optimized and customized together to achieve diverse energy, performance, cost andsize requirements of different classes of applications. MOSART achieves this by:(i) Providing platform support for management of abstract data structures includingmiddleware services and a run-time data manager for NoC based communicationinfrastructure; (ii) Developing tool support for parallelizing and mapping applicationson the multi-core target platform and customizing the processing cores for theapplication.
|
|
| 3. |
|
|
| 4. |
- Ellervee, Peeter, et al.
(författare)
-
Exploring ASIC Design Space at System Level with a Neural Network Estimator
- 1994
-
Ingår i: Proc. of IEEE ASIC-conference, 1994.
-
Konferensbidrag (refereegranskat)abstract
- Estimators are critical tools in doing architectural level exploration of the design space. We present a novel approach to estimation based on the multilayer perceptron which builds the estimation function during the learning process and thus allows to describe arbitrary complex functions. We also describe how the control data flow graph is encoded for the neural network input and we present results of the first experiments made with realistic design examples.
|
|
| 5. |
|
|
| 6. |
|
|
| 7. |
|
|
| 8. |
|
|
| 9. |
- Hellberg, Lars, et al.
(författare)
-
System oriented VLSI curriculum at KTH
- 1997
-
Ingår i: ; , s. 57-59
-
Konferensbidrag (refereegranskat)abstract
- This paper describes the restructuring of VLSI education at the Royal Institute of Technology (KTH). Changing needs of industry, advances in technology and design methodology has required a significant reorganization of VLSI education with combined emphasis on system issues and associated physical constraints. We present here a course structure which will address, in parallel fashion, the key design issues for future system products
|
|
| 10. |
- Hemani, Ahmed, et al.
(författare)
-
High-level synthesis of control and memory intensive communication systems
- 1995
-
Ingår i: ; , s. 185-191
-
Konferensbidrag (refereegranskat)abstract
- Communication sub-systems that deal with switching, routing and protocol implementation often have their functionality dominated by control logic and interaction with memory. Synthesis of such Control and Memory Intensive Systems (hereafter abbreviated to CMISTs) poses demands that in the past have not been met satisfactorily by general purpose high-level synthesis (HLS) tools and have led to several research efforts to address these demands. In this paper we: characterise CMISTs from the synthesis viewpoint; present a synthesis methodology adapted for CMISTs; present the Operation and Maintenance (OAM) Protocol of the ATM, its modelling in VHDL and synthesis aspects of the VHDL model; present the results of applying the synthesis methodology to the OAM as a test case-the results are compared to that obtained using the not adapted general purpose High-level synthesis tool; prove the efficacy of the proposed synthesis methodology by applying it to an industrial design and comparing our results to the results from two commercial HLS tools and to the results obtained by designing manually at register-transfer level
|
|
