| 1. |
- Abdalla, Suliman A
(author)
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Architecture and circuit design of photon counting readout for X-ray imaging sensors
- 2007
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Licentiate thesis (other academic/artistic)abstract
- Hybrid pixel array detectors for X-ray imaging are based on different technologies for sensor and readout electronics. The readout electronics are based on standard CMOS technologies that are experiencing continuously rapid improvements by means of down-scaling the feature sizes, which in turn lead to higher transistor densities, lower power consumption, and faster circuits. For pixel-array imaging sensors the improvements in CMOS technology opens up new possibilities of integrating more functionality in the pixels for local processing of the sensor data. However, new issues related to the tight integration of both analog and digital processing circuits within the small area of a pixel must also be evaluated. The advantages of down-scaling the CMOS technology can be utilized to increase the spatial resolution by reducing the pixel sizes. Recent research indicates however that the bottleneck in reaching further spatial resolution in X-ray imaging sensors may not be limited by the circuit area occupied by the functions necessary in the pixels, but are instead related to problems associated with charge-sharing of charges generated by the sensor which are distributed over a neighbourhood of pixels and will limit the spatial resolution and lead to a distortion of the energy spectrum. In this thesis a mechanism to be implemented in the readout circuits is proposed in order to suppress the charge-sharing effects. The proposed architecture and its circuit implementation are evaluated with respect to circuit complexity (area) and power consumption. For a photon-counting pixel it is demonstrated that the complete pixel, with charge-sharing suppression mechanism, can be implemented using 300 transistors with an idle power consumption of 2.7μW in a 120nm CMOS technology operating with a 1.2V power supply. The improvements in CMOS technology can also be used for increasing the range of applications for X-ray imaging sensors. In this thesis, an architecture is proposed for multiple energy discrimination, called color X-ray imaging. The proposed solution is the result of balancing the circuit complexity and the image quality. The method is based on color sub-sampling with intensity biasing. For three-level energy discrimination, that corresponds to color imaging systems for visible light with R, G, and B color components, the increase in circuit complexity will be only 20% higher than that for the Bayer method but results in significantly better image quality. As the circuit complexity in the digital processing within each pixel is increased, the digitally induced noise may play an increasingly important role for the signal-to-noise ratio in the measurements. In this thesis an initial study is conducted regarding how the digital switching noise affects the analog amplifiers in the photon-counting pixel.
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| 2. |
- Abdalla, Suliman, et al.
(author)
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Architecture and Circuit Design for Color X-Ray Pixal Array Detector Read-Out Electronics
- 2007
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In: 24th Norchip Conference, 2006. - New York : IEEE conference proceedings. - 9781424407729 ; , s. 271-276
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Conference paper (peer-reviewed)abstract
- This paper proposes an area- and power-efficient implementation of the read-out electronics for color X-ray pixel detectors for imaging. Introducing multiple levels of energy discrimination will increase the complexity of the read-out electronics in each pixel. The proposed architecture has full resolution for the intensity and reduced resolution for the energy spectrum (color), which leads to a good compromise of image quality and circuit complexity. We show that the increase in complexity, compared to single energy-range pixel, will lead to increase in circuit area of less than 20%.
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| 3. |
- Abdalla, Suliman, et al.
(author)
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Circuit Implementation of Mechanism for Charge-Sharing Suppression for Photon-Counting Pixel Arrays
- 2005
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In: 23rd NORCHIP Conference 2005. - : IEEE conference proceedings. - 1424400643 ; , s. 137-140
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Conference paper (peer-reviewed)abstract
- This work proposes an efficient circuit implementation of a mechanism for charge-sharing suppression in photon-counting pixel arrays based on current-mode circuits for the analog parts. The additional circuits needed for charge-sharing suppression in a four-pixel cluster, leads to an increase in power consumption of 36% and only a marginal increase in circuit area. The implemented pixel with window-discrimination, managing charge-sharing in a four-pixel cluster and with an event-counter of 13 bits, consists of 300 transistors and has a power consumption of 2.7 μW when idle. It is implemented in a 120nm CMOS process and the presented results are based on simulations.
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| 4. |
- Adin, Veysi, et al.
(author)
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Tiny Machine Learning for Damage Classification in Concrete Using Acoustic Emission Signals
- 2023
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In: 2023 IEEE International Instrumentation and Measurement Technology Conference (I2MTC). - : IEEE. - 9781665453837
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Conference paper (peer-reviewed)abstract
- Acoustic emission (AE) is a widely used non-destructive test method in structural health monitoring applications to identify the damage type in the material. Usually, the analysis of the AE signal is done by using traditional parameter-based methods. Recently, machine learning methods showed promising results for the analysis of AE signals. However, these machine learning models are complex, slow, and consume significant amounts of energy. To address these limitations and to explore the trade-off between model complexity and the classification accuracy, this paper presents a lightweight artificial neural network model to classify damage types in concrete material using raw acoustic emission signals. The model consists of one hidden layer with four neurons and is trained on a public acoustic emission signal dataset. The created model is deployed to several microcontrollers and the performance of the model is evaluated and compared with a state-of-the-art machine learning model. The model achieves 98.4% accuracy on the test data with only 4019 parameters. In terms of evaluation metrics, the proposed tiny machine learning model outperforms previously proposed models 10 to 1000 times. The proposed model thus enables machine learning in real-time structural health monitoring applications.
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| 5. |
- Adin, Veysi, et al.
(author)
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Tiny Machine Learning for Real-Time Postural Stability Analysis
- 2023
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In: 2023 IEEE Sensors Applications Symposium (SAS). - : IEEE conference proceedings. - 9798350323078
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Conference paper (peer-reviewed)abstract
- Postural sway is a critical measure for evaluating postural control, and its analysis plays a vital role in preventing falls among the elderly. Typically, physiotherapists assess an individual's postural control using tests such as the Berg Balance Scale, Tinetti Test, and time up-and-go test. Sensor-based analysis is available based on devices such as force plates or inertial measurement units. Recently, machine learning methods have demonstrated promising results in the sensor-based analysis of postural control. However, these models are often complex, slow, and energy-intensive. To address these limitations, this study explores the design space of lightweight machine learning models deployable to microcontrollers to assess postural stability. We developed an artificial neural network (ANN) model and compare its performance to that of random forests, gaussian naive bayes, and extra tree classifiers. The models are trained using a sway dataset with varying input sizes and signal-to-noise ratios. The dataset comprises two feature vectors extracted from raw accelerometer data. The developed models are deployed to an ARM Cortex M4-based microcontroller, and their performance is evaluated and compared. We show that the ANN model has 99.03% accuracy, higher noise immunity, and the model performs better with a window size of one second with 590.96 us inference time.
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| 6. |
- Ahmad, Naeem, et al.
(author)
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Model and placement optimization of a sky surveillance visual sensor network
- 2011
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In: Proceedings - 2011 International Conference on Broadband and Wireless Computing, Communication and Applications, BWCCA 2011. - : IEEE Computer Society. - 9781457714559 ; , s. 357-362
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Conference paper (peer-reviewed)abstract
- Visual Sensor Networks (VSNs) are networks which generate two dimensional data. The major difference between VSN and ordinary sensor network is the large amount of data. In VSN, a large number of camera nodes form a distributed system which can be deployed in many potential applications. In this paper we present a model of the physical parameters of a visual sensor network to track large birds, such as Golden Eagle, in the sky. The developed model is used to optimize the placement of the camera nodes in the VSN. A camera node is modeled as a function of its field of view, which is derived by the combination of the lens focal length and camera sensor. From the field of view and resolution of the sensor, a model for full coverage between two altitude limits has been developed. We show that the model can be used to minimize the number of sensor nodes for any given camera sensor, by exploring the focal lengths that both give full coverage and meet the minimum object size requirement. For the case of large bird surveillance we achieve 100% coverage for relevant altitudes using 20 camera nodes per km2 for the investigated camera sensors.
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| 7. |
- Ahmad, Naeem
(author)
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Modelling and optimization of sky surveillance visual sensor network
- 2012
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Licentiate thesis (other academic/artistic)abstract
- A Visual Sensor Network (VSN) is a distributed system of a largenumber of camera sensor nodes. The main components of a camera sensornode are image sensor, embedded processor, wireless transceiver and energysupply. The major difference between a VSN and an ordinary sensor networkis that a VSN generates two dimensional data in the form of an image, whichcan be exploited in many useful applications. Some of the potentialapplication examples of VSNs include environment monitoring, surveillance,structural monitoring, traffic monitoring, and industrial automation.However, the VSNs also raise new challenges. They generate large amount ofdata which require higher processing powers, large bandwidth requirementsand more energy resources but the main constraint is that the VSN nodes arelimited in these resources.This research focuses on the development of a VSN model to track thelarge birds such as Golden Eagle in the sky. The model explores a number ofcamera sensors along with optics such as lens of suitable focal length whichensures a minimum required resolution of a bird, flying at the highestaltitude. The combination of a camera sensor and a lens formulate amonitoring node. The camera node model is used to optimize the placementof the nodes for full coverage of a given area above a required lower altitude.The model also presents the solution to minimize the cost (number of sensornodes) to fully cover a given area between the two required extremes, higherand lower altitudes, in terms of camera sensor, lens focal length, camera nodeplacement and actual number of nodes for sky surveillance.The area covered by a VSN can be increased by increasing the highermonitoring altitude and/or decreasing the lower monitoring altitude.However, it also increases the cost of the VSN. The desirable objective is toincrease the covered area but decrease the cost. This objective is achieved byusing optimization techniques to design a heterogeneous VSN. The core ideais to divide a given monitoring range of altitudes into a number of sub-rangesof altitudes. The sub-ranges of monitoring altitudes are covered by individualsub VSNs, the VSN1 covers the lower sub-range of altitudes, the VSN2 coversthe next higher sub-range of altitudes and so on, such that a minimum cost isused to monitor a given area.To verify the concepts, developed to design the VSN model, and theoptimization techniques to decrease the VSN cost, the measurements areperformed with actual cameras and optics. The laptop machines are used withthe camera nodes as data storage and analysis platforms. The area coverage ismeasured at the desired lower altitude limits of homogeneous as well asheterogeneous VSNs and verified for 100% coverage. Similarly, the minimumresolution is measured at the desired higher altitude limits of homogeneous aswell as heterogeneous VSNs to ensure that the models are able to track thebird at these highest altitudes.
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| 8. |
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| 9. |
- Alfredsson, Jon, 1977-, et al.
(author)
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Basic Speed and Power Properties of Digital Floating-gate Circuits Operating in Subthreshold
- 2005
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In: Proceedings of IFIP VLSI-SOC 2005. - : Edith Cowan Univ. ; , s. 229-232
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Conference paper (peer-reviewed)abstract
- For digital circuits with ultra-low power consumption,floating-gate circuits have been considered to be a techniquepotentially better than standard static CMOS circuits.By having a DC offset on the floating gates, theeffective threshold voltage of the floating-gate transistoris adjusted and the speed and power performance can bealtered. In this paper the basic performance related propertiessuch as power, delay, power-delay product (PDP),and energy-delay product (EDP) for floating-gate circuitsoperating in subthreshold are investigated. Based on circuitsimulations in a 120nm process technology, it isshown that for the best case, the power can be reducedapproximately by one order of magnitude at the expenseof increased delay, while the PDP is more or less constantin comparison to static CMOS. The EDP can be reducedby two orders of magnitude at the expense of reducednoise margins.
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| 10. |
- Alfredsson, Jon, et al.
(author)
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Capacitance Selection for Digital Floating Gate Circuits Operating in Subthreshold
- 2006
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In: Proceedings - IEEE International Symposium on Circuits and Systems. - : IEEE conference proceedings. - 9780780393899 ; , s. 4341-4344
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Conference paper (peer-reviewed)abstract
- For digital circuits with ultra-low power consumption, floating-gate circuits (FGMOS) have been considered to be a potentially better technique than standard static CMOS circuits. By having a DC offset on the floating gates, the effective threshold voltage of the floating-gate transistor is adjusted and the speed and power performance can be altered. In this paper we have investigated how the floating-gate capacitances can be selected to achieve the best performance in floating-gate circuits operating at subthreshold power supply. Based on circuit simulations in a 120nm process technology, it is shown that the EDP offers a reduction of more than one order of magnitude for FGMOS with capacitance selection in comparison to static CMOS circuits. This paper also deals with the possibilities available for trade-offs between lower power consumption and higher speed to achieve a better performance for FGMOS than for static CMOS. The main cost involved in achieving these performance improvements is reduced noise margins
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