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Träfflista för sökning "WFRF:(Nilsson Peter) ;pers:(Torkelson Mats)"

Sökning: WFRF:(Nilsson Peter) > Torkelson Mats

  • Resultat 11-20 av 27
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11.
  • Nilsson, Peter, et al. (författare)
  • CMOS on-chip clock for digital signal processors
  • 1993
  • Ingår i: Electronics Letters. - Stevenage, UK : IET. - 0013-5194 .- 1350-911X. ; 15:8, s. 669-670
  • Tidskriftsartikel (refereegranskat)abstract
    • An on-chip clock for frequencies up to 190 MHz is presented. This clock generator can be used for application specific digital signal processors which are clocked faster than the off-chip system clock. It is useful for both processors with a few cycles per sample or for high frequency bit-serial processors which need a large number of cycles.
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12.
  • Nilsson, Peter, et al. (författare)
  • Method to Save Silicon Area by Increasing the Filter Order
  • 1995
  • Ingår i: Electronics Letters. - 1350-911X. ; 31:6, s. 439-441
  • Tidskriftsartikel (refereegranskat)abstract
    • The authors' intention is to show that there are other criteria when optimising digital filters than minimising the filter order. The final result in the form of minimum silicon area or few machine cycles in a high-speed custom DSP are aims that are important in a custom design process. It is not an axiom that the minimum order of the filter gives the optimum result. Algorithms with trivial coefficients will gain both in area and speed. As an example, they show a wideband digital filter for mobile communication
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14.
  • Olsson, Thomas, et al. (författare)
  • A Digitally Controlled Low-Power Clock Multiplier for Globally Asynchronous Locally Synchronous Designs
  • 2000
  • Ingår i: The 2000 IEEE International Symposium on Circuits and Systems. Proceedings.. - 0780354826 ; 3, s. 13-16
  • Konferensbidrag (refereegranskat)abstract
    • Partitioning large high-speed globally synchronous ASICs into locally clocked blocks reduces clock skew problems and if handled correctly it also reduces the power consumption. However, to achieve these positive effects, the blocks need on-chip clock generators having properties such as small area and low power consumption. Therefore, a low power, high frequency, small area digitally controlled on-chip clock generator is designed and fabricated using a 0.35 μm process. The clock generator delivers up to 1.15 GHz at 3.3 V supply voltage. At 1 V supply voltage, it delivers up to 92 MHz while consuming 0.16 mW
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  • Resultat 11-20 av 27

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