| 1. |
- Bardizbanyan, Alen, 1986, et al.
(författare)
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Generation and Exploration of Layouts for Area-Efficient Barrel Shifters
- 2010
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Ingår i: Proceedings of IEEE Computer Society Annual Symp. on VLSI (ISVLSI). - 9780769540764 ; , s. 454-455
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Konferensbidrag (refereegranskat)abstract
- Good layout quality is very important in order to obtain efficient Integrated circuits, and custom design methods are thus considered when speed, power, and area requirements are very strict. But since custom design styles require extensive and specialized development resources, automated, less optimal design methods are often chosen. Alternate methods to create efficient layouts may prove useful, especially since custom layout In future technology nodes is associated with prohibitive nonrecurring engineering (NRE) costs. The prototype layout generation environment shown In this paper allows us to define, evaluate and modify fine-grained cell placement strategies for barrel shifters In a quick manner. The three different 90-nm shifter circuit Implementations demonstrated here show a performance that Is on par with circuits harnessing the capabilities offered by conventional tools. Furthermore, this performance is achieved using the least possible die area. For example, a 32-bit fan-out split shifter conventionally laid out and clocked at 1.11 GHz, dissipates 0.37 mW of switching power and occupies an area of 5698 μm2. The same shifter circuit placed using our environment and routed conventionally, equivalently dissipates 0.34 mW, but occupies only 4711 μm2. © 2010 IEEE.
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| 2. |
- Candaele, Bernard, et al.
(författare)
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Mapping Optimisation for Scalable multi-core ARchiTecture : The MOSART approach
- 2010
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Ingår i: Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010. - 9780769540764 ; , s. 518-523
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Konferensbidrag (refereegranskat)abstract
- The project will address two main challenges of prevailing architectures: 1) The global Interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption; 2) The difficulties in programming heterogeneous, multi-core platforms, in particular in dynamically managing data structures in distributed memory. MOSART aims to overcome these through a multi-core architecture with distributed memory organisation, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimised and customised together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: A) Providing platform support for management of abstract data structures Including middleware services and a run-time data manager for NoC based communication infrastructure; 2) Developing tool support for parallelizing and mapping applications on the multi-core target platform and customizing the processing cores for the application.
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| 3. |
- Liu, Ming, et al.
(författare)
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Inter-process communication using pipes in FPGA-based adaptive computing
- 2010
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Ingår i: Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010. - 9780769540764 ; , s. 80-85
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Konferensbidrag (refereegranskat)abstract
- In FPGA-based adaptive computing, Inter-Process Communications (IPC) are required to exchange information among hardware processes which time-multiplex the resources in a same reconfigurable region. In this paper, we use pipes for IPC and analyze the performance in terms of throughput, throughput efficiency and latency in switching contexts. We also present two practical implementations using FPGA BRAM and external DDR memory. Experimental results expose the key role that context switching plays in determining the IPC performance at various pipe sizes and data rates.
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| 4. |
- Rahmani, Amir-Mohammad, et al.
(författare)
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BBVC-3D-NoC : An Efficient 3D NoC Architecture Using Bidirectional Bisynchronous Vertical Channels
- 2010
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Ingår i: IEEE Annual Symposium on VLSI, ISVLSI 2010. - 9780769540764 ; , s. 452-453
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Konferensbidrag (refereegranskat)abstract
- In this paper, a 3D NoC architecture based on Bidirectional Bisynchronous Vertical Channels (BBVC) is proposed as a solution to mitigate area footprints of vertical interconnects. BBVCs, which can be dynamically self-configured to transmit flits in either direction, enable the system to benefit from a high-speed bidirectional channel instead of a pair of unidirectional channels for inter-layer communication. By exploiting the high-speed nature of the vertical links in 3D ICs, this substitution indicates better bandwidth utilization, lower area footprint, and improved routability at each layer. Our results reveal that the proposed architecture helps to achieve up to 47% savings in TSV area footprint at the 65nm technology node.
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