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- Rehnstedt, Carl, et al.
(författare)
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Drive current and threshold voltage control in vertical InAs wrap-gate transistors
- 2008
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Ingår i: Electronics Letters. - : Institution of Engineering and Technology (IET). - 1350-911X .- 0013-5194. ; 44:3, s. 236-237
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Tidskriftsartikel (refereegranskat)abstract
- Results on fabrication and DC-characterisation of vertical InAs nanowire wrap-gate field-effect transistor arrays with a gate length of 50 nm are presented. Each nanowire array was processed into a transistor with a systematic variation in a number of wires and wire diameter over the sample. Extensive studies have been performed on the influence of wire number and diameter on the transistor characteristics due to a high device yield (84%). In particular it is shown that the threshold voltage depends on the wire diameter, with a change in the order of 5 mV/nm. These results show the possibility of changing the transistor characteristics on the sample by altering the wire dimensions, still using only one patterning and growth sequence.
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- Sigurd, Bengt, et al.
(författare)
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Språköversättning
- 1962
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Ingår i: Datamaskiner och deras användning inom vetenskap, administration och språköversättning. - 0346-2994. ; 2
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Bokkapitel (övrigt vetenskapligt/konstnärligt)
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- Sigurd, Bengt, et al.
(författare)
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Språköversättning
- 1976
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Ingår i: Den förlängda intelligensen : om datorer och databehandling - om datorer och databehandling. - 9140039544
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Bokkapitel (övrigt vetenskapligt/konstnärligt)
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| 7. |
- Thelander, Claes, et al.
(författare)
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Vertical enhancement-mode InAs nanowire field-effect transistor with 50-nm wrap gate
- 2008
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Ingår i: IEEE Electron Device Letters. - 0741-3106. ; 29:3, s. 206-208
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Tidskriftsartikel (refereegranskat)abstract
- We present results on fabrication and de characterization of vertical InAs nanowire wrap-gate field-effect transistor arrays with a gate length of 50 nm. The wrap gate is defined by evaporation of 50-nm Cr onto a 10-nm-thick HfO2 gate dielectric, where the gate is also separated from the source contact with a 100-nm SiOx spacer layer. For a drain voltage of 0.5 V, we observe a normalized transconductance of 0.5 S/mm, a subthreshold slope around 90 mV/dec, and a threshold voltage just above 0 V. The highest observed normalized on current is 0.2 A/mm, with an off current of 0.2 mA/mm. These devices show a considerable improvement compared to previously reported vertical InAs devices with SiNx gate dielectrics.
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