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| 2. |
- Beshkova, Milena, 1975-, et al.
(författare)
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Structural Properties of 3C-SiC Grown by Sublimation Epitaxy
- 2009
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Ingår i: ECSCRM2009,2009. - Materials Science Forum Vols. 615-617 : Trans Tech Publications. - 9780878493340 ; , s. 181-184
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Konferensbidrag (refereegranskat)abstract
- The present paper deals with morphological and structural investigation of 3C-SiC layers grown by sublimation epitaxy on on axis 6H-SiC(0001) at source temperature 2000 °C, under vacuum conditions (<10-5 mbar) and different temperature gradients in the range of 5-8 °C/mm. The layer grown at a temperature gradient 6 °C/mm has the largest average domain size of 0.4 mm2 assessed by optical microscope in transmission mode. The rocking curve full width at half maximum (FWHM) of (111) reflection is 43 arcsec which suggests good crystalline quality. The AFM image of the same layer shows steps with height 0.25 nm and 0.75 nm which are characteristic of a stacking fault free 3C-SiC surface and c-axis repeat height, respectively.
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| 3. |
- Ciechonski, Rafal, 1976-, et al.
(författare)
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Evaluation of MOS structures processed on 4H–SiC layers grown by PVT epitaxy
- 2005
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Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 49:12, s. 1917-1920
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Tidskriftsartikel (refereegranskat)abstract
- MOS capacitors have been fabricated on 4H–SiC epilayers grown by physical vapor transport (PVT) epitaxy. The properties were compared with those on similar structures based on chemical vapor deposition (CVD) layers. Capacitance–voltage (C–V) and conductance measurements (G–V) were performed in the frequency range of 1 kHz to 1 MHz and also at temperatures up to 475 K. Detailed investigations of the PVT structures indicate a stable behaviour of the interface traps from room temperature up to 475 K. The amount of positive oxide charge QO is 6.83 × 109 cm−2 at room temperature and decreases with temperature increase. This suggests that the processed devices are temperature stable. The density of interface states Dit obtained by Nicollian–Brews conductance method is lower in the structure based on the PVT grown sample.
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| 4. |
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| 5. |
- Ewing, D.J., et al.
(författare)
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Inhomogeneous electrical characteristics in 4H-SiC Schottky diodes
- 2007
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Ingår i: Semiconductor Science and Technology. - : IOP Publishing. - 0268-1242 .- 1361-6641. ; 22:12, s. 1287-1291
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Tidskriftsartikel (refereegranskat)abstract
- Hundreds of current-voltage (I-V) measurements of Ni, Pt and Ti Schottky diodes on 4H-SiC were conducted at low applied voltages. The SiC substrates contained homoepitaxial layers grown by either chemical vapor deposition or sublimation. While near-ideal contacts were fabricated on all samples, a significant percentage of diodes (∼7%-50% depending on the epitaxial growth method and the diode size) displayed a non-ideal, or inhomogeneous, barrier height. These 'non-ideal' diodes occurred regardless of growth technique, pre-deposition cleaning method, or contact metal. In concurrence with our earlier reports in which the non-ideal diodes were modeled as two Schottky barriers in parallel, the lower of the two Schottky barriers, when present, was predominantly centered at one of the three values: ∼0.60, 0.85 or 1.05 eV. The sources of these non-idealities were investigated using electron-beam- induced current (EBIC) and deep-level transient spectroscopy (DLTS) to determine the nature and energy levels of the defects. DLTS revealed a defect level that corresponds with the low- (non-ideal) barrier height, at ∼0.60 eV. It was also observed that the I-V characteristics tended to degrade with increasing deep-level concentration and that inhomogeneous diodes tended to contain defect clusters. Based on the results, it is proposed that inhomogeneities, in the form of one or more low-barrier height regions within a high-barrier height diode, are caused by defect clusters that locally pin the Fermi level. © 2007 IOP Publishing Ltd.
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| 6. |
- Gällström, Andreas, 1978-, et al.
(författare)
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Influence of Cooling Rate after High Temperature Annealing on Deep Levels in High-Purity Semi-Insulating 4H-SiC
- 2007
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Ingår i: Materials Science Forum, vol. 556-557. - : Trans Tech Publications. ; , s. 371-
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Konferensbidrag (refereegranskat)abstract
- The influence of different cooling rates on deep levels in 4H-SiC after high temperature annealing has been investigated. The samples were heated from room temperature to 2300°C, followed by a 20 minutes anneal at this temperature. Different subsequent cooling sequences down to 1100°C were used. The samples have been investigated using photoluminescence (PL) and IV characteristics. The PL intensities of the silicon vacancy (VSi) and UD-2, were found to increase with a faster cooling rate.
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| 7. |
- Hens, Philip, et al.
(författare)
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P- and n-type doping in SiC sublimation epitaxy using highly doped substrates
- 2009
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Ingår i: ECSCRM2008,2008. - Materials Science Forum Vols. 615-617 : Trans Tech Publications. - 9780878493340 ; , s. 85-88
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Konferensbidrag (refereegranskat)abstract
- The co-doping of nitrogen and aluminum has been studied in the sublimation epitaxy growth process. It is shown that the doping may be tuned from n-type to p-type by effect of substrate doping, growth face and volume of the growth crucible. The co-doped layers show a nearly ideal I V characteristic and luminescence at room temperature.
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| 8. |
- Jokubavicius, Valdas, 1983-, et al.
(författare)
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Silicon Carbide Surface Cleaning and Etching
- 2018
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Ingår i: Advancing Silicon Carbide Electronics Technology I. - : Materials Research Forum LLC. - 9781945291845 - 9781945291852 ; , s. 1-26
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Bokkapitel (refereegranskat)abstract
- Silicon carbide (SiC) surface cleaning and etching (wet, electrochemical, thermal) are important technological processes in preparation of SiC wafers for crystal growth, defect analysis or device processing. While removal of organic, particulate and metallic contaminants by chemical cleaning is a routine process in research and industrial production, the etching which, in addition to structural defects analysis, can also be used to modify wafer surface structure, is very interesting for development of innovative device concepts. In this book chapter we review SiC chemical cleaning and etching procedures and present perspectives of SiC etching for new device development.
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