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| 3. |
- McHugo, S. A., et al.
(författare)
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Nanometer–scale metal precipitates in multicrystalline silicon solar cells
- 2001
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Ingår i: Journal of Applied Physics. - : AIP Publishing. - 0021-8979 .- 1089-7550. ; 89:8, s. 4282-4288
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Tidskriftsartikel (refereegranskat)abstract
- In this study, we have utilized characterization methods to identify the nature of metal impurityprecipitates in low performance regions of multicrystalline silicon solar cells. Specifically, we haveutilized synchrotron-based x-ray fluorescence and x-ray absorption spectromicroscopy to study theelemental and chemical nature of these impurity precipitates, respectively. We have detectednanometer-scale precipitates of Fe, Cr, Ni, Cu, and Au in multicrystalline silicon materials from avariety of solar cell manufacturers. Additionally, we have obtained a direct correlation between theimpurity precipitates and regions of low light-induced current, providing direct proof that metalimpurities play a significant role in the performance of multicrystalline silicon solar cells.Furthermore, we have identified the chemical state of iron precipitates in the low-performanceregions. These results indicate that the iron precipitates are in the form of oxide or silicatecompound. These compounds are highly stable and cannot be removed with standard siliconprocessing, indicating remediation efforts via impurity removal need to be improved. Futureimprovements to multicrystalline silicon solar cell performance can be best obtained by inhibitingoxygen and metal impurity introduction as well as modifying thermal treatments during crystalgrowth to avoid oxide or silicate formation.
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| 5. |
- Fayed, A. A., et al.
(författare)
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A high speed, low voltage CMOS offset comparator
- 2003
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Ingår i: Analog Integrated Circuits and Signal Processing. - 0925-1030 .- 1573-1979. ; 36:3, s. 267-272
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Tidskriftsartikel (refereegranskat)abstract
- A high speed, low voltage offset comparator is presented. No common mode tracking circuit is used and the offset is added without compromising the high input impedance nature of the circuit. The circuit operates at 480 Mbps with 3.0-3.6 V and 1.6-2.0 V supplies and -40 to 125 degreesC temperature range on a typical 0.5 mum technology.
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| 6. |
- Aktas, A., et al.
(författare)
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Pad de-embedding in RF CMOS
- 2001
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Ingår i: IEEE Circuits & Devices. - : Institute of Electrical and Electronics Engineers (IEEE). - 8755-3996 .- 1558-1888. ; 17:3, s. 8-11
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Tidskriftsartikel (refereegranskat)abstract
- Welcome to The Chip! We remain committed to bringing you material you can use in your work and research. We solicit your contributions and input on what we present here. Material or short articles on chip design tips, modeling and characterization techniques, yield enhancement, packaging, and test are welcome, as well as news on new chips and start-ups, mergers, acquisitions, partnerships in the microchip business, etc. Please continue to e-mail us at ismail@ee.eng.ohio-state.edu or ntan@globespan.net. In this column, we discuss techniques for RF pad layout and de-embedding, a topic of great interest particularly for implementing radio frequency (RF) circuits in mainstream CMOS technology. Happy reading!
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| 7. |
- Alzaher, H. A., et al.
(författare)
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A CMOS fully balanced second-generation current conveyor
- 2003
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Ingår i: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print). - : Institute of Electrical and Electronics Engineers (IEEE). - 1057-7130 .- 1558-125X. ; 50:6, s. 278-287
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Tidskriftsartikel (refereegranskat)abstract
- The design and implementation of a high performance CMOS fully balanced second-generation current conveyor (FBCCII) is presented. The proposed circuit is essential to extend the use of the CCII based circuits to integrated circuits (ICs) applications. The circuit is developed by applying the current sensing technique to a fully balanced version of a differential difference amplifier (DDA). A low power class AB circuit realization is implemented in a 1.2-mum CMOS technology and its different characteristics are measured. Design examples of realizing fully balanced variable gain amplifiers (VGAs) and a bandpass filter based on the proposed FBCCII are given. Experimental results of the proposed circuits are included.
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| 8. |
- Alzaher, H. A., et al.
(författare)
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A CMOS highly linear channel-select filter for 3G multistandard integrated wireless receivers
- 2002
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Ingår i: IEEE Journal of Solid-State Circuits. - : Institute of Electrical and Electronics Engineers (IEEE). - 0018-9200 .- 1558-173X. ; 37:1, s. 27-37
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Tidskriftsartikel (refereegranskat)abstract
- A new approach for designing digitally programmable CMOS integrated baseband filters is presented. The proposed technique provides a systematic method for designing filters exhibiting high linearity and low power. A sixth-order Butterworth low-pass filter with 14-bit bandwidth tuning range is designed for implementing the baseband channel-select filter in an integrated multistandard wireless receiver. The filter consumes a current of 2.25 mA from a 2.7-V supply and occupies an area of 1.25 mm(2) in a 0.5-mum chip. The proposed filter design achieves high spurious free dynamic ranges (SFDRs) of 92 dB for PDC (IS-54),89 dB for GSM, 84 dB for IS-95, and 80 dB for WCDMA.
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| 9. |
- Alzaher, H. A., et al.
(författare)
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CMOS digitally programmable filter for multi-standard wireless receivers
- 2000
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Ingår i: Electronics Letters. - : Institution of Engineering and Technology (IET). - 0013-5194 .- 1350-911X. ; 36:2, s. 133-135
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Tidskriftsartikel (refereegranskat)abstract
- A technique for designing digitally programmable CMOS integrated filters for multi-standard wireless receivers is presented. The technique exhibits the wide frequency range of the transconductance amplifier filters while offering improved linearity. It utilises digitally controlled current followers to provide precise frequency characteristics that can be tuned over a wide range. A digitally tuned lowpass filter is designed for implementing the channel-select filter in the baseband chain of a multi-standard CMOS wireless receiver. Simulation and experimental results obtained from a 1.2 mu m chip show a programmable frequency response covering the IS-54, GSM, IS-95 and WCDMA wireless standards.
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| 10. |
- Alzaher, H. A., et al.
(författare)
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CMOS fully differential second-generation current conveyor
- 2000
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Ingår i: Electronics Letters. - : Institution of Engineering and Technology (IET). - 0013-5194 .- 1350-911X. ; 36:13, s. 1095-1096
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Tidskriftsartikel (refereegranskat)abstract
- The design of a CMOS fully differential second generation current conveyor is presented. The proposed circuit was designed to incorporate the current sensing technique into a fully differential version of a differential difference amplifier (DDA). A low power class AB circuit realisation has been implemented in 1.2 mu m CMOS technology. A variable gain amplifier (VGA) designed to incorporate the circuit has been shown to exhibit constant, low power consumption and constant, wide bandwidth at different gain settings. Experimental results of the proposed circuits are presented.
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