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- Subramanyan, Pramod, et al.
(författare)
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Generation of Minimal Leakage Input Vectors with Constrained NBTI Degradation
- 2009
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Ingår i: <em>7th IEEE East-West Design & Test Symposium (EWDTS), Moscow, Russia, September 18-21, 2009.</em>. ; , s. 1-4
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Konferensbidrag (refereegranskat)abstract
- Technology scaling has caused Negative Bias Temperature Instability (NBTI) to emerge as a major circuit reliability concern. Simultaneously leakage power is becoming a greater fraction of the total power dissipated by logic circuits. As both NBTI and leakage power are highly dependent on vectors applied at the circuit’s inputs, they can be minimized by applying carefully chosen input vectors during periods when the circuit is in standby or idle mode. Unfortunately input vectors that minimize leakage power are not the ones that minimize NBTI degradation, so there is a need for a methodology to generate input vectors that minimize both of these variables.This paper proposes such a systematic methodology for the generation of input vectors which minimize leakage power under the constraint that NBTI degradation does not exceed a specified limit. These input vectors can be applied at the primary inputs of a circuit when it is in standby/idle mode and are such that the gates dissipate only a small amount of leakage power and also allow a large majority of the transistors on critical paths to be in the “recovery” phase of NBTI degradation. The advantage of this methodology is that allowing circuit designers to constrain NBTI degradation to below a specified limit enables tighter guardbanding, increasing performance. Our methodology guarantees that the generated input vector dissipates the least leakage power among all the input vectors that satisfy the degradation constraint.We formulate the problem as a zero-one integer linear program and show that this formulation produces input vectors whose leakage power is within 1% of a minimum leakage vector selected by a search algorithm and simultaneously reduces NBTI by about 5.75% of maximum circuit delay as compared to the worst case NBTI degradation. Our paper also proposes two new algorithms for the identification of circuit paths that are affected the most by NBTI degradation. The number of such paths identified by our algorithms are an order of magnitude fewer than previously proposed heuristics.
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- Subramanyan, Pramod, et al.
(författare)
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Power Efficient Redundant Execution for Chip Multiprocessors
- 2009
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Ingår i: <em>Workshop on Dependable and Secure Nanocomputing, Lisbon, Portugal, June 29, 2009.</em>. ; , s. 1-6
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Konferensbidrag (refereegranskat)abstract
- This paper describes the design of a power efficient microarchitecture for transient fault detection in chip multiprocessors (CMPs) We introduce a new per-core dynamic voltage and frequency scaling (DVFS) algorithm for our architecture that significantly reduces power dissipation for redundant execution with a minimal performance overhead. Using cycle accurate simulation combined with a simple first order power model, we estimate that our architecture reduces dynamic power dissipation in the redundant core by an mean value of 79% and a maximum of 85% with an associated mean performance overhead of only 1.2%.
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- Tudu, Jaynarayan T., et al.
(författare)
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On Minimization of Peak Power for Scan Circuit during Test
- 2009
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Ingår i: <em>Proceedings of the 14th IEEE European Test Symposium, ETS 2009</em>. - 9780769537030 ; , s. 25-30
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Konferensbidrag (refereegranskat)abstract
- Scan circuit generally causes excessive switching activity compared to normal circuit operation. The higher switching activity in turn causes higher peak power supply current which results into supply voltage droop and eventually yield loss. This paper proposes an efficient methodology for test vector re-ordering to achieve minimum peak power supported by the given test vector set. The proposed methodology also minimizes average power under the minimum peak power constraint. A methodology to further reduce the peak power, below the minimum supported peak power, by inclusion of minimum additional vectors is also discussed. The paper defines the lower bound on peak power for a given test set. The results on several benchmarks shows that it can reduce peak power by up to 27%.
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- Vinay, N.S., et al.
(författare)
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Thermal Aware Test Scheduling for Stacked Multi-Chip-Modules
- 2009
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Ingår i: <em>DATE 2009 Friday Workshop on 3D Integration - Technology, Architecture, Design, Automation, and Test, Nice, France, April 20-24, 2009.</em>.
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Konferensbidrag (refereegranskat)
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