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Träfflista för sökning "WFRF:(Weerasekera D) srt2:(2006-2009)"

Sökning: WFRF:(Weerasekera D) > (2006-2009)

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1.
  • Grange, Matt, et al. (författare)
  • Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh
  • 2009
  • Ingår i: 2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION. - San Francisco : IEEE conference proceedings. - 9781424445110 ; , s. 345-351
  • Konferensbidrag (refereegranskat)abstract
    • The physical performance of a 3-Dimensional Network-on-Chip (NoC) mesh architecture employing through silicon vias (TSV) for vertical connectivity is investigated with a cycle-accurate RTL simulator. The physical latency and area impact of TSVs, switches, and the on-chip interconnect is evaluated to extract the maximum signaling speeds through the switches, horizontal and vertical network links. The relatively low parasitics of TSVs compared to the on-chip 2-D interconnect allow for higher signaling speeds between chip layers. The system-level impact on overall network performance as a result of clocking vertical packets at a higher rate through the TSV interconnect is simulated and reported.
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2.
  • Weerasekera, Roshan, et al. (författare)
  • Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime
  • 2006
  • Ingår i: Int. Workshop Syst. Level Interconnect Predict. SLIP. - New York, NY, USA : ACM. - 1595932550 - 9781595932556 ; , s. 113-120
  • Konferensbidrag (refereegranskat)abstract
    • In this paper we propose a smart repeater that consumes less energy and is suitable for driving global interconnections in nanometre technologies. When there is coupling between interconnects, the effective capacitance of a given wire is a function not only of the physical geometry, but also the relative switching pattern described by the bits on the wire in question (the victim) and the adjacent wires (aggressors). The drive strength of a traditional repeater is static, resulting in a spread of the propagation delay, with the repeater strength being essentially too much for every bit pattern other than the worst-case pattern. In the proposed SMART repeater, the drive strength is dynamically altered depending on the relative bit pattern, by partitioning it into a Main Driver and Assistant Driver. For a higher effective load capacitance both drivers switch, while for a lower effective capacitance the assistant driver is quiet. By disconnecting part of the repeater when it is not needed, the total load capacitance to the previous stage is reduced, resulting in reduced energy consumption for those instances. It is shown that the potential average saving in energy can be as much 15% with a 18% jitter reduction over a traditional repeater for typical global wire lengths in nanometre technologies.
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