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Sökning: db:Swepub > Jantsch Axel > (2005-2009)

  • Resultat 61-70 av 107
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61.
  • Lu, Zhonghai, et al. (författare)
  • Using synchronizers for refining synchronous communication onto Hardware/Software architectures
  • 2007
  • Ingår i: RSP 2007. - : IEEE Computer Society. - 9780769528342 ; , s. 143-149
  • Konferensbidrag (refereegranskat)abstract
    • We have presented a formal set of synchronization components called synchronizers for refining synchronous communication onto HW/SW codesign architectures. Such an architecture imposes asynchronous communication between HW-HW SW-SW and HW-SW components. The synchronizers enable local synchronization, thus satisfy the synchronization requirement of a typical IP core. In this paper we present their implementations in HW, SW and HW/SW as well as their application. To validate our concepts, we conduct a case study on a Nios FPGA that comprises a processor memory and custom logic. The final HW/SW implementation achieves equivalent performance to pure HW implementation. Our prototyping experience suggests that the synchronizers can be standardized as library modules and effectively separate the design of computation from that of communication.
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62.
  • Marinissen, E. J., et al. (författare)
  • Conference reports : DATE 07 workshop on diagnostic services in NoCs
  • 2007
  • Ingår i: IEEE Design & Test of Computers. - 0740-7475 .- 1558-1918. ; 24:5, s. 510-
  • Tidskriftsartikel (refereegranskat)abstract
    • 1. TTTC Forum honors Melvin Breuer - at the 2006 International Test Conference, a half-day technical forum was held to honor Melvin Breuer, a pioneer in the areas of VLSI design automation and test; 2. Design flow and methodology addressed at SOC 2006 - The International Symposium on System-on-Chip took place on 13-16 November 2006 in Tampere, Finland. The theme was "SoC Design Flow and Methodology." There were nine high-caliber, 45-minute invited talks, covering different approaches and application areas in SoC design.
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63.
  • Mathaikutty, Deepak A., et al. (författare)
  • SML-Sys : a functional framework with multiple models of computation for modeling heterogeneous system
  • 2008
  • Ingår i: Design automation for embedded systems. - : Springer Science and Business Media LLC. - 0929-5585 .- 1572-8080. ; 12:1-2, s. 1-30
  • Tidskriftsartikel (refereegranskat)abstract
    • System-on-Chip and other complex distributed hardware/software systems contain heterogeneous components. High-level modeling of such systems require frameworks that provide designers with the ability to express concepts of models of computation (MoC)s as modeling constructs. Many system-level modeling frameworks and corresponding modeling notations such as Ptolemy II and SystemC-H facilitate multi-MoC modeling but are based on imperative programming languages (C++, Java, etc). In such frameworks, the computation and communication aspects between the components of models get intertwined thereby hindering its amenability to formal analysis. In this work, we illustrate function-based semantic definitions of MoCs, which are formulated in a functional framework called SML-Sys. We illustrate through a number of examples how to create system models using this functional programming paradigm.
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64.
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65.
  • Mathaikutty, Deepak Abraham, et al. (författare)
  • UMoC++ : A C++-Based Multi-MoC Modeling Environment
  • 2006
  • Ingår i: Advances in Design and Specification Languages for SoCs. - : Springer Publishing Company. ; , s. 115-130
  • Konferensbidrag (refereegranskat)abstract
    • System-on-chip (SoC) and other complex distributed hardware/software systemscontain heterogeneous components that necessitate frameworks capable of expressingheterogeneous models of computation (MoCs) for modeling their functionalities.System-level design languages (SLDLs) that facilitate multi-MoCmodeling should have well-defined semantics and should be readily subjectedto formal analysis to handle the design complexity. As a result, we follow themulti-MoC paradigm based on timing abstraction and functional parameterizationsthat have rigorous denotational semantics, which are compliant to functionalidioms as shown in functional frameworks such as ForSyDe and SML-Sys.However, functional frameworks are not widely used in the industry due toissues related to efficiency and interoperability with other widely used SLDLs.This imposes a requirement for an imperative language-based implementationof these generic MoCs that offers all the advantages of the underlying formalsemantics. In this chapter, we formulate the basis for having generic MoCs in animperative language and describe the implementation of an untimed modelingframework called UMoC++.
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66.
  • Mathaikutty, Deepak A., et al. (författare)
  • UMoC plus plus : A C plus plus -based Multi-MoC modeling environment
  • 2006
  • Ingår i: APPLICATIONS OF SPECIFICATION AND DESIGN LANGUAGES FOR SOCS. - Dordrecht : SPRINGER. ; , s. 115-130
  • Konferensbidrag (refereegranskat)abstract
    • System-on-chip (SoC) and other complex distributed hardware/software systems contain heterogeneous components that necessitate frameworks capable of expressing heterogeneous models of computation (MoCs) for modeling their functionalities. System-level design languages (SLDLs) that facilitate multi-MoC modeling should have well-defined semantics and should be readily subjected to formal analysis to handle the design complexity. As a result, we follow the multi-MoC paradigm based on timing abstraction and functional parameterizations that have rigorous denotational semantics, which are compliant to functional idioms as shown in functional frameworks such as ForSyDe and SML-Sys. However, functional frameworks are not widely used in the industry due to issues related to efficiency and interoperability with other widely used SLDLs. This imposes a requirement for an imperative language-based implementation of these generic MoCs that offers all the advantages of the underlying formal semantics. In this chapter, we formulate the basis for having generic MoCs in an imperative language and describe the implementation of an untimed modeling framework called UMoC++.
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67.
  • Mathaikutty, Deepak, et al. (författare)
  • EWD : A metamodeling driven customizable multi-MoC system modeling framework
  • 2007
  • Ingår i: ACM Transactions on Design Automation of Electronic Systems. - : Association for Computing Machinery (ACM). - 1084-4309 .- 1557-7309. ; 12:3, s. 1255470-
  • Tidskriftsartikel (refereegranskat)abstract
    • We present the EWD design environment and methodology, a modeling and simulation framework suited for complex and heterogeneous embedded systems with varying degrees of expressibility and modeling fidelity. This environment promotes the use of multiple models of computation (MoCs) to support heterogeneity and metamodeling for conformance tests of syntactic and static semantics during the process of modeling. Therefore, EWD is a multiple MoC rnodeling and simulation framework that ensures conformance of the MoC formalisms during model construction using a metamodeling approach. In addition, EWD provides a suite of translation tools that generate executable models for two simulation frameworks to demonstrate its language-independent modeling framework. The EWD methodology uses the Generic Modeling Environment for customization of the MoC-specific modeling syntax into a visual representation. To embed the execution semantics of the MoCs into the models, we have built parsing and translation tools that leverage an XML-based interoperability language. This interoperability language is then translated into executable Standard ML or Haskell models that can also be analyzed by existing simulation frameworks such as SML-Sys or ForSyDe. In summary, EWD is a metamodeling driven multitarget design environment with multi-MoC modeling capability.
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68.
  • Millberg, Mikael, et al. (författare)
  • A study of NoC Exit Strategies
  • 2007
  • Ingår i: NOCS 2007. - 9780769527734 ; , s. 217-217
  • Konferensbidrag (refereegranskat)abstract
    • The throughput of a network is limited due to several interacting components. Analysing simulation results made it clear that the component that was worth attacking was the exit bandwidth between the network and the connected resources. The obvious approach is to increase this bandwidth; the benefit is a higher throughput of the network and a significant lowering of the buffer requirements at the entry points of the network this because worst case scenarios now happens at a higher injection rate. The result we present shows significant differences in throughput as well as in average and worst case latency.
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69.
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70.
  • Millberg, Mikael, et al. (författare)
  • Increasing NoC performance and utilisation using a Dual Packet Exit strategy
  • 2007
  • Ingår i: DSD 2007. - LOS ALAMITOS : IEEE COMPUTER SOC. - 9780769529783 ; , s. 511-518
  • Konferensbidrag (refereegranskat)abstract
    • When designing a network the use of buffers is inevitable. Buffers are used at the entry point, inside and at the exits of the network. The usage of these buffers significantly changes the performance of the system. as a whole. In order to enhance the buffer utilisation the concept of letting more than one packet exit the network at every switch each clock cycle is introduced - Dual Packet Exit (DPE). The approach is tried on a 4x4 and a 6x6 mesh. We demonstrate the buffers used in combination with different routing strategies for best effort performance. The result we present shows a 50% reduction in terms of worst case latency and a 30% reduction in terms of average latency as well as an increased throughput both from a system and network perspective. We define the term Operational Efficiency as a measure of the network efficiency and show that it increases by roughly 20 % with the DPE technique.
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