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(author)
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Exploring ASIC Design Space at System Level with a Neural Network Estimator
- 1994
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In: Proc. of IEEE ASIC-conference, 1994.
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Conference paper (peer-reviewed)abstract
- Estimators are critical tools in doing architectural level exploration of the design space. We present a novel approach to estimation based on the multilayer perceptron which builds the estimation function during the learning process and thus allows to describe arbitrary complex functions. We also describe how the control data flow graph is encoded for the neural network input and we present results of the first experiments made with realistic design examples.
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- Eslami Kiasari, Abbas, et al.
(author)
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A Framework for Designing Congestion-Aware Deterministic Routing
- 2010
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In: NoCArc '10 Proceedings of the Third International Workshop on Network on Chip Architectures. - New York, NY, USA : ACM. - 9781450303972 ; , s. 45-50
-
Conference paper (peer-reviewed)abstract
- In this paper, we present a system-level Congestion-Aware Routing (CAR) framework for designing minimal deterministic routing algorithms. CAR exploits the peculiarities of the application workload to spread the load evenly across the network. To this end, we first formulate an optimization problem of minimizing the level of congestion in the network and then use the simulated annealing heuristic to solve this problem. The proposed framework assures deadlock-free routing, even in the networks without virtual channels. Experiments with both synthetic and realistic workloads show the effectiveness of the CAR framework. Results show that maximum sustainable throughput of the network is improved by up to 205% for different applications and architectures.
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| 48. |
- Eslami Kiasari, Abbas, et al.
(author)
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A Heuristic Framework for Designing and Exploring Deterministic Routing Algorithm for NoCs
- 2013
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In: Algorithms in Networks-on-Chip. - New York, NY : Springer. - 9781461482734 ; , s. 21-39
-
Book chapter (peer-reviewed)abstract
- In this chapter, we present a system-level framework for designing minimal deterministic routing algorithms for Networks-on-Chip (NoCs) that are customized for a set of applications. To this end, we first formulate an optimization problem of minimizing average packet latency in the network and then use the simulated annealing heuristic to solve this problem. To estimate the average packet latency we use a queueing-based analytical model which can capture the burstiness of the traffic. The proposed framework does not require virtual channels to guarantee deadlock freedom since routes are extracted from an acyclic channel dependency graph. Experiments with both synthetic and realistic workloads show the effectiveness of the approach. Results show that maximum sustainable throughput of the network is improved for different applications and architectures.
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| 49. |
- Eslami Kiasari, Abbas, et al.
(author)
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An Analytical Latency Model for Networks-on-Chip
- 2013
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In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. - 1063-8210 .- 1557-9999. ; 21:1, s. 113-123
-
Journal article (peer-reviewed)abstract
- We propose an analytical model based on queueing theory for delay analysis in a wormhole-switched network-on-chip (NoC). The proposed model takes as input an application communication graph, a topology graph, a mapping vector, and a routing matrix, and estimates average packet latency and router blocking time. It works for arbitrary network topology with deterministic routing under arbitrary traffic patterns. This model can estimate per-flow average latency accurately and quickly, thus enabling fast design space exploration of various design parameters in NoC designs. Experimental results show that the proposed analytical model can predict the average packet latency more than four orders of magnitude faster than an accurate simulation, while the computation error is less than 10% in non-saturated networks for different system-on-chip platforms.
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| 50. |
- Eslami Kiasari, Abbas, et al.
(author)
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Analytical approaches for performance evaluation of networks-on-chip
- 2012
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In: CASES'12 - Proceedings of the 2012 ACM International Conference on Compilers, Architectures and Synthesis for Embedded Systems, Co-located with ESWEEK. - New York, NY, USA : ACM. - 9781450314244 ; , s. 211-212
-
Conference paper (peer-reviewed)abstract
- This tutorial reviews four popular mathematical formalisms - dataflow analysis, schedulability analysis, network calculus, and queueing theory - and how they have been applied to the analysis of Network-on-Chip (NoC) performance. We review the basic concepts and results of each formalism and provide examples of how they have been used in on-chip communication performance analysis. The tutorial also discusses the respective strengths and weaknesses of each formalism, their suitability for a specific purpose, and the attempts that have been made to bridge these analytical approaches. Finally, we conclude the tutorial by discussing open research issues.
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