| 1. |
- Alvandpour, Atila, 1960-, et al.
(författare)
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Conditional burn-in keeper for dynamic circuits
- 2004
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Patent (populärvet., debatt m.m.)abstract
- A dynamic circuit with a conditional keeper for burn-in. In the described embodiments, a conditional keeper is provided which is active only during the burn-in test, where the conditional keeper is sized larger than the standard keepers so as to compensate for additional leakage currents in the dynamic circuit.
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| 2. |
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| 3. |
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| 4. |
- Alvandpour, Atila, 1960-, et al.
(författare)
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Differential charge transfer sense ampliifier
- 2004
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Patent (populärvet., debatt m.m.)abstract
- A sense amplifier for reading memory cells in a SRAM, the sense amplifier comprising two gate-biased pMOSFETs, each corresponding to a selected bitline. The gates of the two gate-biased pMOSFETs have their gates biased to a bias voltage, their sources coupled to the selected bitlines via column-select transistors, and their drains coupled via pass transistors to the two ports of two cross-coupled inverters, the cross-coupled inverters forming a latch. After a selected bitline pair has been pre-charged and the pre-charge phase ends, one of the two gate-biased pMOSFETs quickly goes into its subthreshold region as one of the bitlines discharges through its corresponding memory cell, thereby cutting off the bitline's capacitance from the sense amplifier. When the pass transistors are enabled, the other of the two pMOSFETs allows a significant bitline charge to transfer via its corresponding pass transistor to its corresponding port, whereas a relatively much smaller charge is transferred to the other port. This charge transfer scheme allows a differential voltage to quickly develop at the ports, thereby providing a fast latch and read operation with reduced power consumption. Bitline voltage swing may also be reduced to reduce power consumption.
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| 5. |
- Alvandpour, Atila, 1960-
(författare)
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Domino circuit
- 2002
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Patent (populärvet., debatt m.m.)abstract
- A domino logic circuit contained within an integrated circuit includes a dynamic logic circuit and an intermediate logic circuit. The intermediate logic circuit includes a pull-up transistor having a source terminal coupled to a source voltage line and an n-block transistor having a source terminal connected to a low ground voltage lin
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| 6. |
- Alvandpour, Atila, 1960-
(författare)
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Enhanced domino circuit
- 2004
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Patent (populärvet., debatt m.m.)abstract
- A domino logic circuit contained within an integrated circuit includes a dynamic logic circuit and an intermediate logic circuit. The intermediate logic circuit includes a pull-up transistor having a source terminal coupled to a source voltage line and an n-block transistor having a source terminal connected to a low ground voltage line.
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| 7. |
- Alvandpour, Atila, 1960-, et al.
(författare)
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Fast dual-rail dynamic logic style
- 2005
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Patent (populärvet., debatt m.m.)abstract
- A dual-rail static logic gate with a self cut-off mechanism is disclosed. In an embodiment, the output of the first rail is coupled to the input of the pull-up device of the second rail and vice versa. The cross-coupling allows the self cut-off mechanism of the static gate to function properly and provides for components which have lower capacitance than conventional static gates. The lower capacitance results in a faster static gate.
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| 8. |
- Alvandpour, Atila, 1960-, et al.
(författare)
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Fast static receiver with input dependent inversion threshold.
- 2006
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Patent (populärvet., debatt m.m.)abstract
- A static receiver having a first inversion threshold for received signals undergoing a HIGH-to-LOW transition, and a second inversion threshold for received signals undergoing a LOW-to-HIGH transition, where the first inversion threshold is greater than the second inversion threshold. One embodiment comprises a static receiver, a pFET, and a nFET, where when a HIGH-to-LOW transition is being received at the receiver's input port, the pFET is coupled to the input port so as to contribute to raising the inversion threshold, and when a LOW-to-HIGH transition is being received at the input port, the nFET is coupled to the input port so as to contribute to lowering the inversion threshold. Other embodiments are described and claimed.
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| 9. |
- Alvandpour, Atila, 1960-, et al.
(författare)
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Flash (II)-Domino : a fast dual-rail dynamic logic style
- 2004
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Patent (populärvet., debatt m.m.)abstract
- A dual-rail static logic gate with a self cut-off mechanism is disclosed. In an embodiment, the output of the first rail is coupled to the input of the pull-up device of the second rail and vice versa. The cross-coupling allows the self cut-off mechanism of the static gate to function properly and provides for components which have lower capacitance than conventional static gates. The lower capacitance results in a faster static gate.
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| 10. |
- Alvandpour, Atila, 1960-, et al.
(författare)
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Integrated circuits bus architecture including a full-swing, clocked, commongate receiver for fast on-chip signal transmission
- 2002
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Patent (populärvet., debatt m.m.)abstract
- An integrated circuit (IC) bus architecture is disclosed. The bus architecture includes a receiver for fast on-chip signal transmission. The receiver includes a first gate device having one terminal connected to a voltage source and a gate terminal connectable to receive a sense signal. A second gate device includes one terminal connected to another terminal of the first gate device, a gate terminal connectable to receive the sense signal and another terminal serving as an input terminal of the receiver and connectable to an interconnect bus to receive input signals from other components on the IC chip. The receiver also includes a third gate device having one terminal connected to a voltage source and another terminal serving as an output terminal of the receiver and connected to the other terminal of the first gate device. The receiver further includes an inverter having an input terminal connected to the output of the receiver and having an output terminal connected to a gate terminal of the third gate device. The input of the receiver is capable of being pre-discharged to a low signal and the output of the receiver is capable of being pre-charged to a high signal for substantially instantaneous transmission of input signals received by the receiver.
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