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- Eilert, Johan
(författare)
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ASIP for Wireless Communication and Media
- 2010
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- While general purpose processors reach both high performance and high application flexibility, this comes at a high cost in terms of silicon area and power consumption. In systems where high application flexibility is not required, it is possible to trade off flexibility for lower cost by tailoring the processor to the application to create an Application Specific Instruction set Processor (ASIP) with high performance yet low silicon cost. This thesis demonstrates how ASIPs with application specific data types can provide efficient solutions with lower cost. Two examples are presented, an audio decoder ASIP for audio and music processing and a matrix manipulation ASIP for MIMO radio baseband signal processing. The audio decoder ASIP uses a 16-bit floating point data type to reduce the size of the data memory to about 60% of other solutions that use a 32-bit data type. Since the data memory occupies a major part of the silicon area, this has a significant impact on the total silicon area, and thereby also the static and dynamic power consumption. The data width reduction can be done without any noticeable artifacts in the decoded audio due to the natural masking effect ofthe human ear. The matrix manipulation SIMD ASIP is designed to perform various matrix operations such as matrix inversion and QR decomposition of small complex-valued matrices. This type of processing is found in MIMO radio baseband signal processing and the matrices are typically not larger than 4x4. There have been solutions published that use arrays of fixed-function processing elements to perform these operations, but the proposed ASIP performs the computations in less time and with lower hardware cost. The matrix manipulation ASIP data path uses a floating point data type to avoid data scaling issues associated with fixed point computations, especially those related to division and reciprocal calculations, and it also simplifies the program control flow since no special cases for certain inputs are needed which is especially important for SIMD architectures. These two applications were chosen to show how ASIPs can be a suitable alternative and match the requirements for different types of applications, to provide enough flexibility and performance to support different standards and algorithms with low hardware cost.
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| 2. |
- Nilsson, Anders, 1980-
(författare)
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Design of multi-standard baseband processors
- 2005
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Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Efficient programmable baseband processors are important in order to enable true multi-standard radio platforms and software defined radio systems. The ever changing wireless network industry also requires flexible and versatile baseband processors to be able to adapt quickly to new and updated standards. The convergence of mobile communication devices and systems require multi-standard capabilities in the processing devices. The processors do not only need the capability to handle differences in a single standard, often there is a great need to cover several completely different modulation methods such as OFDM, CDMA and single carrier modulation with the same processing device. All this requires a programmable baseband processor because a pure fixed-function ASIC solution is not flexible enough. Furthermore, ASIC solutions for multi-standard baseband processing are less area efficient than their programmable counterparts since processing resources cannot efficiently be shared between different operations and standards. This project was initiated for the above mentioned reason as a continuation of a previous baseband processor project at the research group. Accordingly, this thesis is devoted to the design of area efficient, low clock rate, fully programmable baseband processors. A reduction of the clock rate will simplify the design of the processor as well as save power in the application. Since most multi-standard processing devices will be used in a mobile environment, low power is essential. Normally, extra computing resources must be added to a system designed for low clock rate operation compared to a regular solution, resulting in a higher area and complexity of the chip. In this project effort has been made to create efficient base architectures maintaining a low area and clock rate while also maintaining flexibility and processing capability. At the same time design methods for the required DSP execution units within the processor have been developed.Usually general baseband processing includes many tasks such as error control coding/ decoding, interleaving, scrambling etc, however in this thesis because of time and resource limitations, the focus is on the symbol related processing, although the bit manipulation and forward error correction tasks are also studied regarding acceleration.
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| 3. |
- Olausson, Mikael, 1973-
(författare)
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Hardware for speech and audio coding
- 2004
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Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- While the Micro Processors (MPUs) as a general purpose CPU are converging (into Intel Pentium), the DSP processors are diverging. In 1995, approximately 50% of the DSP processors on the market were general purpose processors, but last year only 15% were general purpose DSP processors on the market. The reason general purpose DSP processors fall short to the application specific DSP processors is that most users want to achieve highest performance under minimized power consumption and minimized silicon costs. Therefore, a DSP processor must be an Application Specific Instruction set Processor (ASIP) for a group of domain specific applications.An essential feature of the ASIP is its functional acceleration on instruction level, which gives the specific instruction set architecture for a group of applications. Hardware acceleration for digital signal processing in DSP processors is essential to enhance the performance while keeping enough flexibility. In the last 20 years, researchers and DSP semiconductor companies have been working on different kinds of accelerations for digital signal processing. The trade-off between the performance and the flexibility is always an interesting question because all DSP algorithms are "application specific"; the acceleration for audio may not be suitable for the acceleration of baseband signal processing. Even within the same domain, for example speech CODEC (COder/DECoder), the acceleration for communication infrastructure is different from the acceleration for terminals.Benchmarks are good parameters when evaluating a processor or a computing platform, but for domain specific algorithms, such as audio and speech CODEC, they are not enough. The solution here is to profile the algorithm and from the resulting statistics make the decisions. The statistics also suggest where to start optimizing the implementation of the algorithm. The statistics from the profi ling has been used to improve implementations of speech and audio coding algorithms, both in terms of the cycle cost and for memory efficiency, i.e. code and data memory.In this thesis, we focus on designing memory efficient DSP processors based on instruction level acceleration methods and data type optimization techniques. Four major areas have been attacked in order to speed up execution and reduce memory The first one is instruction level acceleration, where consecutive instructions appear frequently and are merged together. By this merge the code memory size is reduced and execution becomes faster. Secondly, complex addressing schemes are solved by acceleration for address calculations, i.e. dedicated hardware are used for address calculations. The third area, data storage and precision, is speeded up by using a reduced floating point scheme. The number of bits is reduced compared to the normal IEEE 754 floating point standard. The result is a lower data memory requirement, yet enough precision for the application; an mp3 decoder. The fourth contribution is a compact way of storing data in a general CPU. By adding two custom instructions, one load and one store, the data memory efficiency can be improved without making the firmware complex. We have tried to make application specific instruction sets and processors and also tried to improve processors based on an available instruction set.Experiences from this thesis can be used for DSP design for audio and speech applications. They can additionally be used as a reference to a general DSP processor design methodology.
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