| 1. |
- Abbas, Muhammad
(författare)
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On the Implementation of Integer and Non-Integer Sampling Rate Conversion
- 2012
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- The main focus in this thesis is on the aspects related to the implementation of integer and non-integer sampling rate conversion (SRC). SRC is used in many communication and signal processing applications where two signals or systems having different sampling rates need to be interconnected. There are two basic approaches to deal with this problem. The first is to convert the signal to analog and then re-sample it at the desired rate. In the second approach, digital signal processing techniques are utilized to compute values of the new samples from the existing ones. The former approach is hardly used since the latter one introduces less noise and distortion. However, the implementation complexity for the second approach varies for different types of conversion factors. In this work, the second approach for SRC is considered and its implementation details are explored. The conversion factor in general can be an integer, a ratio of two integers, or an irrational number. The SRC by an irrational numbers is impractical and is generally stated for the completeness. They are usually approximated by some rational factor.The performance of decimators and interpolators is mainly determined by the filters, which are there to suppress aliasing effects or removing unwanted images. There are many approaches for the implementation of decimation and interpolation filters, and cascaded integrator comb (CIC) filters are one of them. CIC filters are most commonly used in the case of integer sampling rate conversions and often preferred due to their simplicity, hardware efficiency, and relatively good anti-aliasing (anti-imaging) characteristics for the first (last) stage of a decimation (interpolation). The multiplierless nature, which generally yields to low power consumption, makes CIC filters well suited for performing conversion at higher rate. Since these filters operate at the maximum sampling frequency, therefore, are critical with respect to power consumption. It is therefore necessary to have an accurate and efficient ways and approaches that could be utilized to estimate the power consumption and the important factors that are contributing to it. Switching activity is one such factor. To have a high-level estimate of dynamic power consumption, switching activity equations in CIC filters are derived, which may then be used to have an estimate of the dynamic power consumption. The modeling of leakage power is also included, which is an important parameter to consider since the input sampling rate may differ several orders of magnitude. These power estimates at higher level can then be used as a feed-back while exploring multiple alternatives.Sampling rate conversion is a typical example where it is required to determine the values between existing samples. The computation of a value between existing samples can alternatively be regarded as delaying the underlying signal by a fractional sampling period. The fractional-delay filters are used in this context to provide a fractional-delay adjustable to any desired value and are therefore suitable for both integer and non-integer factors. The structure that is used in the efficient implementation of a fractional-delay filter is know as Farrow structure or its modifications. The main advantage of the Farrow structure lies in the fact that it consists of fixed finite-impulse response (FIR) filters and there is only one adjustable fractional-delay parameter, used to evaluate a polynomial with the filter outputs as coefficients. This characteristic of the Farrow structure makes it a very attractive structure for the implementation. In the considered fixed-point implementation of the Farrow structure, closed-form expressions for suitable word lengths are derived based on scaling and round-off noise. Since multipliers share major portion of the total power consumption, a matrix-vector multiple constant multiplication approach is proposed to improve the multiplierless implementation of FIR sub-filters.The implementation of the polynomial part of the Farrow structure is investigated by considering the computational complexity of different polynomial evaluation schemes. By considering the number of operations of different types, critical path, pipelining complexity, and latency after pipelining, high-level comparisons are obtained and used to short list the suitable candidates. Most of these evaluation schemes require the explicit computation of higher order power terms. In the parallel evaluation of powers, redundancy in computations is removed by exploiting any possible sharing at word level and also at bit level. As a part of this, since exponents are additive under multiplication, an ILP formulation for the minimum addition sequence problem is proposed.
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| 2. |
- Afzal, Nadeem
(författare)
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Complexity and Power Reduction in Digital Delta-Sigma Modulators
- 2014
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- A number of state-of-the-art low power consuming digital delta-sigma modulator (ΔΣ) architectures for digital-to-analog converters (DAC) are presented in this thesis. In an oversampling ΔΣ DAC, the primary job of the modulator is to reduce the word length of the digital control signal to the DAC and spectrally shape the resulting quantization noise. Among the ΔΣ topologies, error-feedback modulators (EFM) are well suited for so called digital to digital modulation.In order to meet the demands, various modifications to the conventional EFM architectures have been proposed. It is observed that if the internal and external digital signals of the EFM are not properly scaled then not only the design itself but also the signal processing blocks placed after it, may be over designed. In order to avoid the possible wastage of resources, a number of scaling criteria are derived. In this regard, the total number of signal levels of the EFM output is expressed in terms of the input scale, the order of modulation and the type of the loop filter.Further on, it is described that the architectural properties of a unit element-based DAC allow us to move some of the digital processing of the EFM to the analog domain with no additional hardware cost. In order to exploit the architectural properties, digital circuitry of an arbitrary-ordered EFM is split into two parts: one producing the modulated output and another producing the filtered quantization noise. The part producing the modulated output is removed after representing the EFM output with a set of encoded signals. For both the conventional and the proposed EFM architectures, the DAC structure remains unchanged. Thus, savings are obtained since the bits to be converted are not accumulated in the digital domain but instead fed directly to the DAC.A strategy to reduce the hardware of conventional EFMs has been devised recently that uses multiple cascaded EFM units. We applied the similar approach but used several cascaded modified EFM units. The compatibility issues among the units (since the output of each proposed EFM is represented by the set of encoded signals) are resolved by a number of architectural modifications. The digital processing is distributed among each unit by splitting the primary input bus. It is shown that instead of cascading the EFM units, it is enough to cascade their loop filters only. This leads not only to area reduction but also to the reduction of power consumption and critical path.All of the designs are subjected to rigorous analysis and are described mathematically. The estimates of area and power consumption are obtained after synthesizing the designs in a 65 nm standard cell library provided by the foundry.
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| 3. |
- Andersson, Niklas, 1975-
(författare)
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Design of Integrated Building Blocks for the Digital/Analog Interface
- 2015
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- The integrated circuit has, since it was invented in the late 1950's, undergone a tremendous development and is today found in virtually all electric equipment. The small feature size and low production cost have made it possible to implement electronics in everyday objects ranging from computers and mobile phones to smart prize tags. Integrated circuits are typically used for data communication, signal processing and data storage. Data is usually stored in digital format but signal processing can be performed both in the digital and in the analog domain. For best performance, the right partition of signal processing between the analog and digital domain must be used. This is made possible by data converters converting data between the domains. A device converting an analog signal into a digital representation is called an analog-to-digital converter (ADC) and a device converting digital data into an analog representation is called a digital-to-analog converter (DAC). In this work we present research results on these data converters and the results are compiled in three different categories. The first contribution is an error correction technique for DACs called dynamic element matching, the second contribution is a power efficient time-to-digital converter architecture and the third is a design methodology for frequency synthesis using digital oscillators.The accuracy of a data converter, i.e., how accurate data is converted, is often limited by manufacturing errors. One type of error is the so-called matching error and in this work we investigate an error correction technique for DACs called dynamic element matching (DEM). If distortion is limiting the performance of a DAC, the DEM technique increases the accuracy of the DAC by transforming the matching error from being signal dependent, which results in distortion, to become signal independent noise. This noise can then be spectrally shaped or filtered out and hereby increasing the overall resolution of the system. The DEM technique is investigated theoretically and the theory is supported by measurement results from an implemented 14-bit DAC using DEM. From the investigation it is concluded that DEM increases the performance of the DAC when matching errors are dominating but has less effect at conversion speeds when dynamic errors dominate.The next contribution is a new time-to-digital converter (TDC) architecture. A TDC is effectively an ADC converting a time difference into a digital representation. The proposed architecture allows for smaller and more power efficient data conversion than previously reported and the implemented TDC prototype is smaller and more power efficient as compared to previously published TDCs in the same performance segment.The third contribution is a design methodology for frequency synthesis using digital oscillators. Digital oscillators generate a sinusoidal output using recursive algorithms. We show that the performance of digital oscillators, in terms of amplitude and frequency stability, to a large extent depends on the start conditions of the oscillators. Further we show that by selecting the proper start condition an oscillator can be forced to repeat the same output sequence over and over again, hence we have a locked oscillator. If the oscillator is locked there is no drift in amplitude or frequency which are common problems for recursive oscillators not using this approach. To find the optimal start conditions a search algorithm has been developed which has been thoroughly tested in simulations. The digital oscillator output is used for test signal generation for a DAC or used to generate tones with high spectral purity using DACs.
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| 4. |
- Blad, Anton, 1981-
(författare)
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Low Complexity Techniques for Low Density Parity Check Code Decoders and Parallel Sigma-Delta ADC Structures
- 2011
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Since their rediscovery in 1995, low-density parity-check (LDPC) codes have received wide-spread attention as practical capacity-approaching code candidates. It has been shown that the class of codes can perform arbitrarily close to the channel capacity, and LDPC codes are also used or suggested for a number of important current and future communication standards. However, the problem of implementing an energy-efficient decoder has not yet been solved. Whereas the decoding algorithm is computationally simple, with uncomplicated arithmetic operations and low accuracy requirements, the random structure and irregularity of a theoretically well-defined code does not easily allow efficient VLSI implementations. Thus the LDPC decoding algorithm can be said to be communication-bound rather than computation-bound.In this thesis, a modification to the sum-product decoding algorithm called earlydecision decoding is suggested. The modification is based on the idea that the values of the bits in a block can be decided individually during decoding. As the sumproduct decoding algorithm is a soft-decision decoder, a reliability can be defined for each bit. When the reliability of a bit is above a certain threshold, the bit can be removed from the rest of the decoding process, and thus the internal communication associated with the bit can be removed in subsequent iterations. However, with the early decision modification, an increased error probability is associated. Thus, bounds on the achievable performance as well as methods to detect graph inconsistencies resulting from erroneous decisions are presented. Also, a hybrid decoder achieving a negligible performance penalty compared to the sum-product decoder is presented. With the hybrid decoder, the internal communication is reduced with up to 40% for a rate-1/2 code with a length of 1152 bits, whereas increasing the rate allows significantly higher gains.The algorithms have been implemented in a Xilinx Virtex 5 FPGA, and the resulting slice utilization and energy dissipation have been estimated. However, due to increased logic overhead of the early decision decoder, the slice utilization increases from 14.5% to 21.0%, whereas the logic energy dissipation reduction from 499 pJ to 291 pJ per iteration and bit is offset by the clock distribution power, increased from 141 pJ to 191 pJ per iteration and bit. Still, the early decision decoder shows a net 16% estimated decrease of energy dissipation.
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| 5. |
- Qureshi, Fahad, 1978-
(författare)
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Optimization of Rotations in FFTs
- 2012
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- The aims of this thesis are to reduce the complexity and increasethe accuracy of rotations carried out inthe fast Fourier transform (FFT) at algorithmic and arithmetic level.In FFT algorithms, rotations appear after every hardware stage, which are alsoreferred to as twiddle factor multiplications.At algorithmic level, the focus is on the development and analysisof FFT algorithms. With this goal, a new approach based on binary tree decompositionis proposed. It uses the Cooley Tukey algorithm to generate a large number ofFFT algorithms. These FFT algorithms have identical butterfly operations and data flow but differ inthe value of the rotations. Along with this, a technique for computing the indices of the twiddle factors based on the binary tree representation has been proposed. We have analyzed thealgorithms in terms of switching activity, coefficient memory size, number of non-trivial multiplicationsand round-off noise. These parameters have impact on the power consumption, area, and accuracy of the architecture.Furthermore, we have analyzed some specific cases in more detail for subsets of the generated algorithms.At arithmetic level, the focus is on the hardware implementation of the rotations.These can be implemented using a complex multiplier,the CORDIC algorithm, and constant multiplications. Architectures based on the CORDIC and constant multiplication use shift and add operations, whereas the complex multiplication generally uses four real multiplications and two adders.The sine and cosine coefficients of the rotation angles fora complex multiplier are normally stored in a memory.The implementation of the coefficient memory is analyzed and the best possible approaches are analyzed.Furthermore, a number of twiddle factor multiplication architectures based on constant multiplications is investigated and proposed. In the first approach, the number of twiddle factor coefficients is reduced by trigonometric identities. By considering the addition aware quantization method, the accuracy and adder count of the coefficients are improved. A second architecture based on scaling the rotations such that they no longer have unity gain is proposed. This results in twiddle factor multipliers with even lower complexity and/or higher accuracy compared to the first proposed architecture.
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| 6. |
- Sheikh, Zaka Ullah, 1967-
(författare)
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Efficient Realizations of Wide-Band and Reconfigurable FIR Systems
- 2012
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Complexity reduction is one of the major issues in today’s digital system designfor many obvious reasons, e.g., reduction in area, reduced power consumption,and high throughput. Similarly, dynamically adaptable digital systems requireflexibility considerations in the design which imply reconfigurable systems, wherethe system is designed in such a way that it needs no hardware modificationsfor changing various system parameters. The thesis focuses on these aspects ofdesign and can be divided into four parts.The first part deals with complexity reduction for non-frequency selectivesystems, like differentiators and integrators. As the design of digital processingsystems have their own challenges when various systems are translated from theanalog to the digital domain. One such problem is that of high computationalcomplexity when the digital systems are intended to be designed for nearly fullcoverage of the Nyquist band, and thus having one or several narrow don’t-carebands. Such systems can be divided in three categories namely left-band systems,right-band systems and mid-band systems. In this thesis, both single-rate andmulti-rate approaches together with frequency-response masking techniques areused to handle the problem of complexity reduction in non-frequency selectivefilters. Existing frequency response masking techniques are limited in a sensethat they target only frequency selective filters, and therefore are not applicabledirectly for non-frequency selective filters. However, the proposed approachesmake the use of frequency response masking technique feasible for the non-frequency filters as well.The second part of the thesis addresses another issue of digital system designfrom the reconfigurability perspective, where provision of flexibility in the designof digital systems at the algorithmic level is more beneficial than at any otherlevel of abstraction. A linear programming (minimax) based technique forthe coefficient decimation FIR (finite-length impulse response) filter design isproposed in this part of thesis. The coefficient decimation design method findsuse in communication system designs in the context of dynamic spectrum accessand in channel adaptation for software defined radio, where requirements can bemore appropriately fulfilled by a reconfigurable channelizer filter. The proposedtechnique provides more design margin compared to the existing method whichcan in turn can be traded off for complexity reduction, optimal use of guardbands, more attenuation, etc.The third part of thesis is related to complexity reduction in frequencyselective filters. In context of frequency selective filters, conventional narrow-band and wide-band frequency response masking filters are focused, where variousoptimization based techniques are proposed for designs having a small number ofnon-zero filter coefficients. The use of mixed integer linear programming (MILP)shows interesting results for low-complexity solutions in terms of sparse andnon-periodic subfilters.Finally, the fourth part of the thesis deals with order estimation of digitaldifferentiators. Integral degree and fractional degree digital differentiators areused in this thesis work as representative systems for the non-frequency selectivefilters. The thesis contains a minimax criteria based curve-fitting approach fororder estimation of linear-phase FIR digital differentiators of integral degree upto four.
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