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Träfflista för sökning "L773:0733 8724 ;pers:(Larsson Edefors Per 1967)"

Sökning: L773:0733 8724 > Larsson Edefors Per 1967

  • Resultat 1-8 av 8
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1.
  • Anet Neto, Luiz, et al. (författare)
  • Considerations on the Use of Digital Signal Processing in Future Optical Access Networks
  • 2020
  • Ingår i: Journal of Lightwave Technology. - 0733-8724 .- 1558-2213. ; 38:3, s. 598-607
  • Tidskriftsartikel (refereegranskat)abstract
    • In this invited paper, we address the impacts of the rise of signal processing for increased capacity per wavelength and better receiver sensitivities in next generation optical access networks. We start by recalling the main channel limitations of currently deployed intensity modulated, directly detected passive optical networks. Then, with the intention of providing a benchmarking of signal processing approaches used in communication systems other than optical access, we provide a historic perspective on how digital signal processing emerged in copper access systems and we evaluate powerful techniques envisaged for future mobile generation in both air interface and radio access networks. We also assess signal processing in the light of multi-vendor interoperability by providing insights on burst mode operation and the needed protocol and monitoring procedures. Interoperability with regard to optical transceivers is also considered. Last but not least, we evaluate power consumption of digital signal processing and forward error correction solutions used in disruptive, coherent transmission approaches.
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2.
  • Börjeson, Erik, 1984, et al. (författare)
  • Energy-Efficient Implementation of Carrier Phase Recovery for Higher-Order Modulation Formats
  • 2021
  • Ingår i: Journal of Lightwave Technology. - 0733-8724 .- 1558-2213. ; 39:2, s. 505-510
  • Tidskriftsartikel (refereegranskat)abstract
    • We introduce circuit implementations of one- and two-stage carrier phase recovery (CPR) for 256QAM coherent optical receivers. We describe in detail the optimizations of algorithms, such as modified Viterbi-Viterbi (mVV), blind phase search (BPS), and principal component-based phase estimation (PCPE), that are required to develop energy-efficient CPR circuits and show how design parameter settings and limited fixed-point resolution affect the SNR penalty. 30-GBaud CPR circuit netlists synthesized in a 22-nm CMOS process technology allow us to study trade-offs between energy per bit and SNR penalty. We show that it is possible to reach an energy dissipation of around 1 pJ/bit at an SNR penalty of 0.6 dB for two-stage PCPE+BPS and mVV+BPS implementations, and that PCPE+BPS is the preferred choice thanks to its smaller area.
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3.
  • Börjeson, Erik, 1984, et al. (författare)
  • Fiber-on-Chip: Digital Emulation of Channel Impairments for Real-Time DSP Evaluation
  • 2023
  • Ingår i: Journal of Lightwave Technology. - 0733-8724 .- 1558-2213. ; 41:3, s. 888-896
  • Tidskriftsartikel (refereegranskat)abstract
    • We describe the Fiber-on-Chip (FoC) approach to verification of digital signal processing (DSP) circuits, where digital models of a fiber-optic communication system are implemented in the same hardware as the DSP under test. The approach can enable cost-effective long-term DSP evaluations without the need for complex optical-electronic testbeds with high-speed interfaces, shortening verification time and enabling deep bit-error rate evaluations. Our FoC system currently contains a digital model of a transmitter generating a pseudo-random bitstream and a digital model of a channel with additive white Gaussian noise, phase noise and polarization-mode dispersion. In addition, the FoC system contains digital features for real-time control of channel parameters, using low-speed communication interfaces, and for autonomous real-time analysis, which enable us to batch multiple unsupervised emulations on the same hardware. The FoC system can target both field-programmable gate arrays, for fast evaluation of fixed-point logic, and application-specific integrated circuits, for accurate power dissipation measurements.
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4.
  • Börjeson, Erik, 1984, et al. (författare)
  • VLSI Implementations of Carrier Phase Recovery Algorithms for M-QAM Fiber-Optic Systems
  • 2020
  • Ingår i: Journal of Lightwave Technology. - 0733-8724 .- 1558-2213. ; 38:14, s. 3616-3623
  • Tidskriftsartikel (refereegranskat)abstract
    • We present circuit implementations of blind phase search (BPS) carrier phase recovery (CPR) for M-QAM coherent optical receivers and highlight some BPS algorithm modifications necessary to obtain efficient VLSI circuits. In addition, we show how three key design parameters (input word length, number of test phases, and type and size of averaging window) affect the resulting implementation. To study design tradeoffs, we develop BPS CPR circuit netlists for a 32-GBaud system, using a 22-nm CMOS process technology: Our implementations reach energy efficiencies of around 1 pJ/bit for 16QAM up to 3 pJ/bit for 256QAM, at an SNR penalty of approximately 0.25 dB at a BER of 10^(−2). Furthermore, we present a circuit implementation of pilot-symbol-aided CPR, reaching 0.38 pJ/bit and 0.34 pJ/bit for 16QAM and 256QAM, respectively, at a slightly higher SNR penalty. The two CPR methods are also evaluated in terms of silicon area and scaling to higher-order modulation formats.
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5.
  • Cushon, Kevin, 1982, et al. (författare)
  • Low-Power 400-Gbps Soft-Decision LDPC FEC for Optical Transport Networks
  • 2016
  • Ingår i: Journal of Lightwave Technology. - 0733-8724 .- 1558-2213. ; 34:18, s. 4304-4311
  • Tidskriftsartikel (refereegranskat)abstract
    • We present forward error correction systems based on soft-decision low-density parity check (LDPC) codes for applications in 100–400-Gbps optical transport networks. These systems are based on the low-complexity “adaptive degeneration” decoding algorithm, which we introduce in this paper, along with randomly-structured LDPC codes with block lengths from 30 000 to 60 000 bits and overhead (OH) from 6.7% to 33%. We also construct a 3600-bit prototype LDPC code with 20% overhead, and experimentally show that it has no error floor above a bit error rate (BER) of 10−15 using a field-programmable gate array (FPGA)-based hardware emulator. The projected net coding gain at a BER of 10−15 ranges from 9.6 dB at 6.7% OH to 11.2 dB at 33% OH. We also present application-specific integrated circuit synthesis results for these decoders in 28 nm fully depleted silicon on insulator technology, which show that they are capable of 400-Gbps operation with energy consumption of under 3 pJ per information bit.
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6.
  • Fougstedt, Christoffer, 1990, et al. (författare)
  • Energy-Efficient High-Throughput VLSI Architectures for Product-Like Codes
  • 2019
  • Ingår i: Journal of Lightwave Technology. - 0733-8724 .- 1558-2213. ; 37:2, s. 477-485
  • Tidskriftsartikel (refereegranskat)abstract
    • Implementing forward error correction (FEC) for modern long-haul fiber-optic communication systems is a challenge, since these high-throughput systems require FEC circuits that can combine high coding gains and energy-efficient operation. We present VLSI decoder architectures for product-like codes for systems with strict throughput and power dissipation requirements. To reduce energy dissipation, our architectures are designed to minimize data transfers in and out of memory blocks, and to use parallel non-iterative component decoders. Using a mature 28-nm VLSI process technology node, we showcase different product and staircase decoder implementations that have the capacity to exceed 1-Tb/s information throughputs with energy efficiencies of around 2 pJ/bit.
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7.
  • Fougstedt, Christoffer, 1990, et al. (författare)
  • Low-Power Low-Latency BCH Decoders for Energy-Efficient Optical Interconnects
  • 2017
  • Ingår i: Journal of Lightwave Technology. - 0733-8724 .- 1558-2213. ; 35:23, s. 5201-5207
  • Tidskriftsartikel (refereegranskat)abstract
    • Since energy dissipation and latency in optical interconnects are of utmost concern, such links are often operated without forward error correction. We propose a low-complexity non-iterative 2-error correcting BCH decoder circuit that significantly relaxes the stringent optical modulation amplitude requirements on the transmitter, which help to reduce laser and laser driver energy. We demonstrate, in a 28-nm CMOS process technology, that the introduction of this BCH circuit in an uncoded link leads to energy-per-bit reductions of 25%, even when impact of code rate on receiver energy dissipation is considered.
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8.
  • Sheikh, Alireza, 1989, et al. (författare)
  • Dispersion Compensation FIR Filter with Improved Robustness to Coefficient Quantization Errors
  • 2016
  • Ingår i: Journal of Lightwave Technology. - 0733-8724 .- 1558-2213. ; 34:22, s. 5110-5117
  • Tidskriftsartikel (refereegranskat)abstract
    • In this paper, we propose a new finite impulseresponse (FIR) filter for chromatic dispersion compensation which is given in closed form. We identify a relation between the out-of-band gain and the in-band error when the filter is implemented with finite-precision arithmetic. In particular, a large out-of-band gain makes the filter more sensitive tocoefficient quantization errors due to finite precision digital signal processing. To improve robustness to coefficient quantization errors, our proposed filter is designed based on confining the out-of-band gain. By means of simulations, we show that our filter outperforms other existing FIR filters. The performance gain improves with increasing modulation order and decreasing number of bits used to represent the filter taps.
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  • Resultat 1-8 av 8

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