| 1. |
- Alam, Ashraful, et al.
(författare)
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Parallelization of the Estimation Algorithm of the 3D Structure Tensor
- 2012
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Ingår i: 2012 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2012. - Piscataway, N.J. : IEEE Press. - 9781467329194 - 9781467329217
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Konferensbidrag (refereegranskat)abstract
- The three dimensional structure tensor algorithm (3D-STA) is often used in image processing applications to compute the optical flow or to detect local 3D structures and their directions. This algorithm is computationally expensive due to many computations that are required to calculate the gradient, the tensor, and to smooth every pixel of the image frames. Therefore, it is important to parallelize the implementation to achieve high performance. In this paper we present two parallel implementations of 3D-STA; namely moderately parallelized and highly parallelized implementation, on a massively parallel reconfigurable array. Finally, we evaluate the performance of the generated code and results are compared with another optical flow implementation. The throughput achieved by the moderately parallelized implementation is approximately half of the throughput of the Optical flow implementation, whereas the highly parallelized implementation results in a 2x gain in throughput as compared to the optical flow implementation. © 2012 IEEE.
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| 2. |
- Almgren Mason, Suzanne, et al.
(författare)
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Bridging Scientific Cultures in a Regional Health Care Context
- 2010
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Ingår i: VIII Triple Helix International Conference on University, Industry and Government Linkages.
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- Embedded Intelligent Systems (EIS) is the joint research field of the four collaborating laboratories at the School of Information Science, Computer and Electrical Engineering (IDE) at Halmstad University. The research of the four labs is integrated into a strong concerted research environment within embedded systems (EIS) - with a perspective reaching from the enabling technology via new system solutions and intelligent applications to end user aspects and business models. It is an expanding research area with many applications, not least ones that exist in everyday life.EIS is an important research environment contributing to the regional Triple Helix innovation system Healthcare Technology which the region has pointed out as a prioritised development sector. With its strong connections to both established and new, expanding firms hived off from the university, the research environment is active in the Healthcare Technology Alliance, a network of around sixty companies, counties and health care providers in south-western Sweden with the aim of developing the region into a leading arena for the development of health technology products and services. Several projects together with these participants concern both research and technology transfer.An integrated gender and gender equality perspective in innovations within the health technology area is necessary in order to be able to meet the needs of an ageing population with quality innovations. The relevancy of a gender perspective is clear in relation to the fact that about 70% of all those older than 75 years are women. Older women are on average cared for in hospital twice as long as men, partly due to differing disease panoramas, but also because men are more often cared for in the home by a woman while the women who live longer more often live alone. With the expansion of home-help and home nursing new needs follow and it is likely that a gender perspective will become necessary for the development of products and services that can make daily life easier for the elderly. The gender perspective also has relevance from the point of view of care staff. New technology is developed for application within the health and care sector where the larger professional groups consist mainly of women. The technology, most often designed by men, is used by women. With this in mind it is clear that an important aspect of good innovations is that the end users are involved in the innovation process.Based on an awareness of the need for a more articulated gender perspective within the research environment, in order to meet the needs expressed above, an application for a gender inclusive R&D project was handed in to the VINNOVA programme Applied Gender Research in Strong Research and Innovation Environments. The G-EIS project (Gender Perspective on Embedded Intelligent Systems - Application in Healthcare Technology) was approved and started in 2009. The project involves researchers from the EIS research environment as well as representatives from companies and the public sector.The project participants are on the whole agreed on the need for a gender perspective in the R&I environment, but struggle with the meeting of two epistemologically opposed theories of science. The understanding within gender studies that research and production both create reality and are informed by it is not always accepted within the areas of natural science. Engineering and other technological sciences not only consider aspects of science to be separate from reality, but also seek positivistic proof in research, something not always possible in the more qualitative research of the social sciences. Researching how these two perspectives meet within this specific project is the topic of this paper.
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| 3. |
- Bengtsson, Jerker, et al.
(författare)
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A configurable framework for stream programming exploration in baseband applications
- 2006
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Ingår i: 2006 IEEE International Parallel & Distributed Processing Symposium. - Piscataway, N.J. : IEEE Press. - 1424400546 ; , s. 8-
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Konferensbidrag (refereegranskat)abstract
- This paper presents a configurable framework to be used for rapid prototyping of stream based languages. The framework is based on a set of design patterns defining the elementary structure of a domain specific language for high-performance signal processing. A stream language prototype for baseband processing has been implemented using the framework. We introduce language constructs to efficiently handle dynamic reconfiguration of distributed processing parameters. It is also demonstrated how new language specific primitive data types and operators can be used to efficiently and machine independently express computations on bitfields and data-parallel vectors. These types and operators yield code that is readable, compact and amenable to a stricter type checking than is common practice. They make it possible for a programmer to explicitly express parallelism to be exploited by a compiler. In short, they provide a programming style that is less error prone and has the potential to lead to more efficient implementations.
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| 4. |
- Bengtsson, Jerker, et al.
(författare)
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A Domain-specific Approach for Software Development on Manycore Platforms
- 2008
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Ingår i: SIGARCH Computer Architecture News. - New York : ACM Press. - 0163-5964 .- 1943-5851. ; 36:5, s. 2-10
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Tidskriftsartikel (refereegranskat)abstract
- The programming complexity of increasingly parallel processors calls for new tools that assist programmers in utilising the parallel hardware resources. In this paper we present a set of models that we have developed as part of a tool for mapping dataflow graphs onto manycores. One of the models captures the essentials of manycores identified as suitable for signal processing, and which we use as target for our algorithms. As an intermediate representation we introduce timed configuration graphs, which describe the mapping of a model of an application onto a machine model. Moreover, we show how a timed configuration graph by very simple means can be evaluated using an abstract interpretation to obtain performance feedback. This information can be used by our tool and by the programmer in order to discover improved mappings.
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| 5. |
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| 6. |
- Bengtsson, Jerker, et al.
(författare)
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Manycore performance analysis using timed configuration graphs
- 2009
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Ingår i: International Symposium on Systems, Architectures, Modeling, and Simulation, 2009. SAMOS '09. - Piscataway, N.J. : IEEE Press. - 9781424445028 ; , s. 108-117
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Konferensbidrag (refereegranskat)abstract
- The programming complexity of increasingly parallel processors calls for new tools to assist programmers in utilising the parallel hardware resources. In this paper we present a set of models that we have developed to form part of a tool which is intended for iteratively tuning the mapping of dataflow graphs onto manycores. One of the models is used for capturing the essentials of manycores that are identified as suitable for signal processing and which we use as target architectures. Another model is the intermediate representation in the form of a timed configuration graph, describing the mapping of a dataflow graph onto a machine model. Moreover, this IR can be used for performance evaluation using abstract interpretation. We demonstrate how the models can be configured and applied in order to map applications on the Raw processor. Furthermore, we report promising results on the accuracy of performance predictions produced by our tool. It is also demonstrated that the tool can be used to rank different mappings with respect to optimisation on throughput and end-to-end latency.
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| 7. |
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| 8. |
- Bengtsson, Jerker
(författare)
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Models and Methods for Development of DSP Applications on Manycore Processors
- 2009
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Advanced digital signal processing systems require specialized high-performance embedded computer architectures. The term high-performance translates to large amounts of data and computations per time unit. The term embedded further implies requirements on physical size and power efficiency. Thus the requirements are of both functional and non-functional nature. This thesis addresses the development of high-performance digital signal processing systems relying on manycore technology. We propose building two-level hierarchical computer architectures for this domain of applications. Further, we outline a tool flow based on methods and analysis techniques for automated, multi-objective mapping of such applications on distributed memory manycore processors. In particular, the focus is put on how to provide a means for tunable strategies for mapping of task graphs on array structured distributed memory manycores, with respect to given application constraints. We argue for code mapping strategies based on predicted execution performance, which can be used in an auto-tuning feedback loop or to guide manual tuning directed by the programmer. Automated parallelization, optimisation and mapping to a manycore processor benefits from the use of a concurrent programming model as the starting point. Such a model allows the programmer to express different types and granularities of parallelism as well as computation characteristics of importance in the addressed class of applications. The programming model should also abstract away machine dependent hardware details. The analytical study of WCDMA baseband processing in radio base stations, presented in this thesis, suggests dataflow models as a good match to the characteristics of the application and as execution model abstracting computations on a manycore. Construction of portable tools further requires a manycore machine model and an intermediate representation. The models are needed in order to decouple algorithms, used to transform and map application software, from hardware. We propose a manycore machine model that captures common hardware resources, as well as resource dependent performance metrics for parallel computation and communication. Further, we have developed a multifunctional intermediate representation, which can be used as source for code generation and for dynamic execution analysis. Finally, we demonstrate how we can dynamically analyse execution using abstract interpretation on the intermediate representation. It is shown that the performance predictions can be used to accurately rank different mappings by best throughput or shortest end-to-end computation latency.
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| 9. |
- Bengtsson, Lars, 1958-, et al.
(författare)
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A high-performance embedded massively parallel processing system
- 1994
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Ingår i: Proceedings of the First International Conference on Massively Parallel Computing Systems (MPCS) The Challenges of General-Purpose and Special-Purpose Computing. - Piscataway, N.J. : IEEE. - 0818663227 - 9780818663222 ; , s. 201-206
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Konferensbidrag (refereegranskat)abstract
- A need to apply the massively parallel computing paradigm in embedded real-time systems is foreseen. Such applications put new demands on massively parallel systems, different from those of general purpose computing. For example, time determinism is more important than maximal throughput, physical distribution is often required, size, power, and I/O are important, and interactive development tools are needed. The paper describes an architecture for high-performance, embedded, massively parallel processing, featuring a large number of nodes physically distributed over a large area. A typical node has thousands of processing elements (PEs) organized in SIMD mode and is the size of the palm of a hand, Intermodule communication over a scalable optical network is described. A combination of wavelength division multiplexing (WDM) and time division multiplexing (TDM) is used. © 1994 IEEE.
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| 10. |
- Bengtsson, Lars, 1958-, et al.
(författare)
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A processor array module for distributed, massively parallel, embedded computing
- 1993
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Ingår i: Microprocessing and Microprogramming. - Amsterdam : Elsevier. - 0165-6074. ; 38:1-5, s. 529-537
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Tidskriftsartikel (refereegranskat)abstract
- With the increased degree of miniaturization resulting from the use of modem VLSI technology and the high communication bandwidth available through optical connections, it is now possible to build massively parallel computers based on distributed modules which can be embedded in advanced industrial products. Examples of such future possibilities are ''action-oriented systems'', in which a network of highly parallel modules perform a multitude of tasks related to perception, cognition, and action. The paper discusses questions of architecture on the level of modules and inter-module communication and gives concrete architectural solutions which meet the demands of typical, advanced industrial real-time applications. The interface between the processors arrays and the all-optical communication network is described in some detail. Implementation issues specifically related to the demand for miniaturization are discussed.
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