| 1. |
- Bengtsson, Lars, 1958-, et al.
(författare)
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REMAP massively parallel computer platform for neural computations
- 1997
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Ingår i: Proceedings of the Third International Conference on Microelectronics for Neural Networks (MicroNeuro’93). ; , s. 47-62
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Konferensbidrag (refereegranskat)abstract
- The REMAP project addresses questions related to the use of massively parallel, distributed computing in embedded systems. Of specific interest is the execution of artificial neural network algorithms on multiple, cooperating processor arrays. This paper concentrates on the recently finished, and currently used, processor array prototype, REMAP-β, of SIMD (Single Instruction stream, Multiple Data streams) type. The architecture and implementation of the computer is described, both its overall structure and its constituent parts. Following this comes a discussion of its use as an architecture laboratory, which stems from the fact that it is implemented using FPGA (Field Programmable Gate Array) circuits. As an architecture laboratory the prototype can be used to implement and evaluate, e.g., various Processing Element (PE) designs. A couple of examples of PE architectures, including one with floating-point support, are given. The mapping of important neural network algorithms on processor arrays of this kind is shown, and possible tuning of the architecture to meet specific processing demands is discussed. Performance figures are given as well as implications for future VLSI implementations of the array.
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| 2. |
- Jonsson, Magnus, 1969-, et al.
(författare)
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Fiber-ribbon pipeline ring network for high-performance distributed computing systems
- 1997
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Ingår i: Proceedings of the Third International Symposium on Parallel Architectures, Algorithms, and Networks, 1997. (I-SPAN '97). - : IEEE. ; , s. 138-143
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Konferensbidrag (refereegranskat)abstract
- In this paper, we propose a high-bandwidth ring network built up with fiber-ribbon point-to-point links. The network has support for both packet switched and circuit switched traffic. Very high throughputs can be achieved in the network due to pipelining, i.e., several packets can be traveling through the network simultaneously but in different segments of the ring. The network can be built today using fiber-optic off-the-shelf components. The increasingly good price/performance ratio for fiber-ribbon links indicates a great success potential for the proposed kind of networks. We also present a massively parallel radar signal processing system with exceptionally high demands on the communication network. An aggregated throughput of tens of Gb/s is needed in this application, and this is achieved with the proposed network.
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| 3. |
- Jonsson, Magnus, 1969-, et al.
(författare)
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Time-deterministic WDM star network for massively parallel computing in radar systems
- 1996
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Ingår i: Proceedings of the Third International Conference on Massively Parallel Processing Using Optical Interconnections. - Los Alamitos, California : IEEE Computer Society Press. - 0818675918 ; , s. 85-93
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Konferensbidrag (refereegranskat)abstract
- In massively parallel computer systems for embedded real-time applications there are normally very high bandwidth demands on the interconnection network. Other important properties are time-deterministic latency and services to guarantee that deadlines are met. In this paper we analyze how these properties vary with the design parameters for a passive optical star network, specifically when used in a massively parallel radar signal processing system. The aggregated bandwidth and computational power of the radar system are approximately 45 Gb/s and 100 GOPS, respectively. The analysis is focused on the medium access control protocol, called TD-TWDMA, for the time and wavelength multiplexed network. It is concluded that the proposed network is very well suited to this kind of signal-processing applications. We also present a new distributed slot-allocation algorithm with real-time properties.
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| 4. |
- Taveniku, Mikael, et al.
(författare)
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A multiple SIMD mesh architecture for multi-channel radar processing
- 1996
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Ingår i: Proceedings of: ICSPAT'96, international conference on signal processing applications & technology, Boston MA, USA, October 7-10. - : Miller Freeman. ; , s. 1421-1427
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Konferensbidrag (refereegranskat)abstract
- In modern and future radar applications there are high demands on the signal processing chain in terms of computational power and generality. At the same time, there are hard size and power consumption constraints. This paper reports on a project whose aim is to find a good scalable computer architecture that is flexible, programmable and as general-purpose as possible without too much performance loss.The proposed architecture consists of multiple SIMD computing modules, each based on a number of small mesh arrays. The modules are fully programmable and work globally as a MIMD machine and locally as SIMD machines. The data network is modular and provides both high bandwidth capacity and fast response. It has a fiber-optic stars topology, and employs time and wavelength division multiplexing, together with a medium access method specially developed for real-time systems.In this paper, we use a radar system with 64 processing channels to illustrate the algorithms and the usage of the processor modules. We show that it is possible to use a machine, consisting of small mesh processor arrays forming larger modules, with good efficiency. The building blocks show good balance between computational power and I/O bandwidth, and the SIMD approach seems good from algorithm-mapping point of view.
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| 5. |
- Taveniku, Mikael, et al.
(författare)
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The VEGA moderately parallel MIMD, moderately parallel SIMD, architecture for high performance array signal processing
- 1998
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Ingår i: Proceedings of the first merged International Parallel Processing Symposium & Symposium on Parallel and Distributed Processing. - Los Alamitos, Calif. : IEEE Computer Press. ; , s. 226-232
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Konferensbidrag (refereegranskat)abstract
- In array radar signal processing applications, the processing demands range from tens of GFLOPS to several TFLOPS. To address this, as well as the, size and power dissipation issues, a special purpose “array signal processing” architecture is proposed. We argue that a combined MIMD-SIMD system can give flexibility, scalability, and programmability as well as high computing density. The MIMD system level, where SIMD modules are interconnected by a fiber-optic real-time network, provides the high level flexibility while the SIMD module level provides the compute density. In this paper we evaluate different design alternatives and show how the VEGA architecture was derived. By examining the applications and the algorithms used, the SIMD mesh processor is found be sufficient. However, the smaller the meshes are the better is the flexibility and efficiency. Then, based on prototype VLSI implementations and on instruction statistics, we find that a relatively large pipelined processing element maximises the performance per area. It is thereby concluded that the small SIMD mesh processor array with powerful processing elements is the best choice. These observations are further exploited in the design of the single-chip SIMD processor array to be included in the MIMD-style overall system. The system scales from 6.4 GFLOPS to several TFLOPS peak performance.
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| 6. |
- Åhlander, Anders, et al.
(författare)
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A multiple SIMD approach to radar signal processing
- 1996
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Ingår i: 1996 IEEE TENCON. - Piscataway, NJ : IEEE Press. - 0780336801 - 0780336798 ; , s. 852-857
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- Next generation radar systems, with phase-controlled array antennas, will have to process data that is many times larger than in current systems. This requires an enormous computing power. Even in a relatively small airborne radar system, with hard size and power consumption constraints, a sustained computing power of 40 GOPS (or 40 GFLOPS, if floating point calculations are used) will be needed to perform only the subset of the calculations known as the space-time adaptive processing, STAP Consequently, there is a need for new parallel computing modules, as well as new overall system architectures and application development environments. In this paper, a modular architecture with highly parallel SIMD-modules is presented as a promising solution, capable of handling STAP. A version of the architecture, equipped with bit-serial floating point PEs, is described and evaluated. Implementation technology aspects are discussed.
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