| 1. |
- Bengtsson, Jerker, et al.
(författare)
-
A configurable framework for stream programming exploration in baseband applications
- 2006
-
Ingår i: 2006 IEEE International Parallel & Distributed Processing Symposium. - Piscataway, N.J. : IEEE Press. - 1424400546 ; , s. 8-
-
Konferensbidrag (refereegranskat)abstract
- This paper presents a configurable framework to be used for rapid prototyping of stream based languages. The framework is based on a set of design patterns defining the elementary structure of a domain specific language for high-performance signal processing. A stream language prototype for baseband processing has been implemented using the framework. We introduce language constructs to efficiently handle dynamic reconfiguration of distributed processing parameters. It is also demonstrated how new language specific primitive data types and operators can be used to efficiently and machine independently express computations on bitfields and data-parallel vectors. These types and operators yield code that is readable, compact and amenable to a stricter type checking than is common practice. They make it possible for a programmer to explicitly express parallelism to be exploited by a compiler. In short, they provide a programming style that is less error prone and has the potential to lead to more efficient implementations.
|
|
| 2. |
- Bengtsson, Jerker, et al.
(författare)
-
A Domain-specific Approach for Software Development on Manycore Platforms
- 2008
-
Ingår i: SIGARCH Computer Architecture News. - New York : ACM Press. - 0163-5964 .- 1943-5851. ; 36:5, s. 2-10
-
Tidskriftsartikel (refereegranskat)abstract
- The programming complexity of increasingly parallel processors calls for new tools that assist programmers in utilising the parallel hardware resources. In this paper we present a set of models that we have developed as part of a tool for mapping dataflow graphs onto manycores. One of the models captures the essentials of manycores identified as suitable for signal processing, and which we use as target for our algorithms. As an intermediate representation we introduce timed configuration graphs, which describe the mapping of a model of an application onto a machine model. Moreover, we show how a timed configuration graph by very simple means can be evaluated using an abstract interpretation to obtain performance feedback. This information can be used by our tool and by the programmer in order to discover improved mappings.
|
|
| 3. |
|
|
| 4. |
- Bengtsson, Jerker, et al.
(författare)
-
Manycore performance analysis using timed configuration graphs
- 2009
-
Ingår i: International Symposium on Systems, Architectures, Modeling, and Simulation, 2009. SAMOS '09. - Piscataway, N.J. : IEEE Press. - 9781424445028 ; , s. 108-117
-
Konferensbidrag (refereegranskat)abstract
- The programming complexity of increasingly parallel processors calls for new tools to assist programmers in utilising the parallel hardware resources. In this paper we present a set of models that we have developed to form part of a tool which is intended for iteratively tuning the mapping of dataflow graphs onto manycores. One of the models is used for capturing the essentials of manycores that are identified as suitable for signal processing and which we use as target architectures. Another model is the intermediate representation in the form of a timed configuration graph, describing the mapping of a dataflow graph onto a machine model. Moreover, this IR can be used for performance evaluation using abstract interpretation. We demonstrate how the models can be configured and applied in order to map applications on the Raw processor. Furthermore, we report promising results on the accuracy of performance predictions produced by our tool. It is also demonstrated that the tool can be used to rank different mappings with respect to optimisation on throughput and end-to-end latency.
|
|
| 5. |
|
|
| 6. |
- Bengtsson, Jerker
(författare)
-
Models and Methods for Development of DSP Applications on Manycore Processors
- 2009
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Advanced digital signal processing systems require specialized high-performance embedded computer architectures. The term high-performance translates to large amounts of data and computations per time unit. The term embedded further implies requirements on physical size and power efficiency. Thus the requirements are of both functional and non-functional nature. This thesis addresses the development of high-performance digital signal processing systems relying on manycore technology. We propose building two-level hierarchical computer architectures for this domain of applications. Further, we outline a tool flow based on methods and analysis techniques for automated, multi-objective mapping of such applications on distributed memory manycore processors. In particular, the focus is put on how to provide a means for tunable strategies for mapping of task graphs on array structured distributed memory manycores, with respect to given application constraints. We argue for code mapping strategies based on predicted execution performance, which can be used in an auto-tuning feedback loop or to guide manual tuning directed by the programmer. Automated parallelization, optimisation and mapping to a manycore processor benefits from the use of a concurrent programming model as the starting point. Such a model allows the programmer to express different types and granularities of parallelism as well as computation characteristics of importance in the addressed class of applications. The programming model should also abstract away machine dependent hardware details. The analytical study of WCDMA baseband processing in radio base stations, presented in this thesis, suggests dataflow models as a good match to the characteristics of the application and as execution model abstracting computations on a manycore. Construction of portable tools further requires a manycore machine model and an intermediate representation. The models are needed in order to decouple algorithms, used to transform and map application software, from hardware. We propose a manycore machine model that captures common hardware resources, as well as resource dependent performance metrics for parallel computation and communication. Further, we have developed a multifunctional intermediate representation, which can be used as source for code generation and for dynamic execution analysis. Finally, we demonstrate how we can dynamically analyse execution using abstract interpretation on the intermediate representation. It is shown that the performance predictions can be used to accurately rank different mappings by best throughput or shortest end-to-end computation latency.
|
|
| 7. |
- Bengtsson, Lars, et al.
(författare)
-
The REMAP Reconfigurable Architecture : a Retrospective
- 2006
-
Ingår i: FPGA Implementations of Neural Networks. - New York : Springer-Verlag New York. - 0387284850 ; , s. 325-360
-
Bokkapitel (refereegranskat)abstract
- The goal of the REMAP project was to gain new knowledge about the design and use of massively parallel computer architectures in embedded real-time systems. In order to support adaptive and learning behavior in such systems, the efficient execution of Artificial Neural Network (ANN) algorithms on regular processor arrays was in focus. The REMAP-β parallel computer built in the project was designed with ANN computations as the main target application area. This chapter gives an overview of the computational requirements found in ANN algorithms in general and motivates the use of regular processor arrays for the efficient execution of such algorithms. REMAP-β was implemented using the FPGA circuits that were available around 1990. The architecture, following the SIMD principle (Single Instruction stream, Multiple Data streams), is described, as well as the mapping of some important and representative ANN algorithms. Implemented in FPGA, the system served as an architecture laboratory. Variations of the architecture are discussed, as well as scalability of fully synchronous SIMD architectures. The design principles of a VLSI-implemented successor of REMAP-β are described, and the paper is concluded with a discussion of how the more powerful FPGA circuits of today could be used in a similar architecture. © 2006 Springer.
|
|
| 8. |
- Bilstrup, Urban, 1971-
(författare)
-
Design Space Exploration of Wireless Multihop Networks
- 2005
-
Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- This thesis explores the feasible design space of wireless multihop networks and identifies fundamental design parameters. In the process of exploring it is important to ignore all details and instead take a holistic view. This means that all protocol details are overseen, all details of radio wave propagation models are overseen and the system is modelled strictly on an architectural level. From a theoretical information perspective, there is a limit to the capacity that a certain bandwidth and a certain signal-to-noise ratio at the receiver can provide. This limit is approximated as a volume in the time-frequency-space domain. A single transmission is represented as an occupied volume in this domain. A wireless multihop network covers a spatial area, and the question is how multiple numbers of transmission volumes can be fit into a given limited spatial area. This volume fitting should be done in order to maximize the overall performance or to trade available resources to favour a specific characteristic in the wireless multihop network. The volume model is used for the design space exploration of a wireless multihop network. It is argued that the fault tolerance and the energy gain achieved in a multihop topology are its strength as compared to a single-hop architecture. It is further shown that the energy gain is achieved at the expense of delay and a greater end-to-end error probability. This indicates that these parameters must be very carefully balanced in order to gain in the global overall performance perspective. It can further be concluded that the overall spatial capacity is increased as a result of the spatial channel reuse in a multihop topology. On the other hand, it is also shown that the multihop topology introduces a rather stringent geometrical capacity limitation when the number of nodes of a wireless multihop network is increased. The dynamics (e.g. node mobility, changing radio channels etc.) of a large scale wireless multihop network is also a limiting factor. The nodes’ mobility creates a knowledge horizon beyond which very little can be known about the present network topology.
|
|
| 9. |
- Bilstrup, Urban, et al.
(författare)
-
The use of clustered wireless multihop networks in industrial settings
- 2007
-
Ingår i: ETFA 2007. - Piscataway, NJ : IEEE Press. - 9781424408252 ; , s. 211-218
-
Konferensbidrag (refereegranskat)abstract
- This paper suggests a cluster collision avoidance mechanism and a dual transceiver architecture to be used in a clustered wireless multihop network. These two contributions make the clustered wireless multihop network the preferred architecture for future industrial wireless networks. The wireless multihop cluster consists of one master and several slaves, where some of the slaves will act as gateways between different clusters. Frequency hopping spread spectrum is used on a cluster level and to avoid frequency collisions between clusters a "neighbor cluster collision avoidance mechanism" is proposed and evaluated through simulations. To break up the dependence between the clusters, introduced by the gateway nodes, each node is equipped with two transceivers. The paper is concluded with a suggestion to use a clustered wireless multihop network with orthogonal hopping sequences for an industrial setting.
|
|
| 10. |
- Bilstrup, Urban, et al.
(författare)
-
Using Dual-Radio Nodes to Enable Quality of Service in a Clustered Wireless Mesh Network
- 2006
-
Ingår i: IEEE Conference on Emerging Technologies and Factory Automation, 2006. ETFA '06. - Piscataway, N.J. : IEEE Press. - 0780397584 ; , s. 54-61
-
Konferensbidrag (refereegranskat)abstract
- In this paper some well established wireless technologies are merged into a new concept solution for a future industrial wireless mesh network. The suggested clustered wireless mesh network can handle probabilistic quality of service guarantees and is based on a dual-radio node architecture using synchronized frequency hopping spread spectrum Bluetooth radios. The proposed architecture gives a heuristic solution to the inter-cluster scheduling problem of gateway nodes in clustered architectures and breaks up the dependence between the local medium access schedules of adjacent clusters. The dual-radio feature also enables higher network connectivity, implying, for example, that a higher link redundancy can be achieved.
|
|
