| 1. |
- Belwal, Chaitanya, et al.
(författare)
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Timing Analysis of the Priority based FRP System
- 2008
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Ingår i: Proceedings Work-In-Progress Session of the 14th Real-Time and Embedded Technology and Applications Symposium. - Lincoln, NE : University of Nebraska–Lincoln, Computer Science and Engineering. ; , s. 89-92
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Konferensbidrag (refereegranskat)abstract
- Kaiabachev, Taha, Zhu [1] have presented a declarative programming paradigm called Functional Reactive Programming, which is based on behaviors and events. An improved system called P-FRP uses fixed priority scheduling for tasks. The system allows for the currently executing lower priority tasks to be rolled back to restoring the original state and allowing a higher priority task to run. These aborted tasks will restart again when no tasks of higher priority are in the queue. Since P-FRP has many applications in the real time domain it is critical to understand the time bound in which the tasks which have been aborted are guaranteed to run, and if the task set is schedulable. In this paper we provide an analysis of the unique execution paradigm of the P-FRP system and study the timing bounds using different constraint variables.1. R. Kaiabachev, W. Taha, A. Zhu, E-FRP with priorities, In the Proceedings of the 7th ACM & IEEE international conference on Embedded software, Pages: 221 - 230, 2007.
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| 2. |
- Gillenwater, Jennifer, et al.
(författare)
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Synthesizable high level hardware descriptions : using statically typed two-level languages to guarantee verilog synthesizability
- 2008
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Ingår i: PEPM '08. - New York, NY, USA : ACM Press. - 9781595939777 ; , s. 13-20
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Konferensbidrag (refereegranskat)abstract
- Modern hardware description languages support code-generation constructs like generate/endgenerate in Verilog. These constructs are intended to describe regular or parameterized hardware designs and, when used effectively, can make hardware descriptions shorter, more understandable, and more reusable. In practice, however, designers avoid these constructs because it is difficult to understand and predict the properties of the generated code. Is the generated code even type safe? Is it synthesizable? What physical resources (e.g. combinatorial gates and flip-flops) does it require? It is often impossible to answer these questions without first generating the fully-expanded code. In the Verilog and VHDL communities, this generation process is referred to as elaboration.This paper proposes a disciplined approach to elaboration in Verilog. By viewing Verilog as a statically typed two-level language, we are able to reflect the distinction between values that are known at elaboration time and values that are part of the circuit computation. This distinction is crucial for determining whether abstractions such as iteration and module parameters are used in a synthesizable manner. To illustrate this idea, we develop a core calculus for Verilog that we call Featherweight Verilog (FV) and an associated static type system. We formally define a preprocessing step analogous to the elaboration phase of Verilog, and the kinds of errors that can occur during this phase. Finally, we show that a well-typed design cannot cause preprocessing errors, and that the result of its expansion is always a synthesizable circuit.
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| 3. |
- Taha, Walid, 1971-
(författare)
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A Gentle Introduction to Multi-stage Programming, Part II
- 2008
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Ingår i: Generative and Transformational Techniques in Software Engineering II. - Berlin : Springer Berlin/Heidelberg. - 9783540886426 - 3540886427 ; , s. 260-290
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- As domain-specific languages (DSLs) permeate into mainstream software engineering, there is a need for economic methods for implementing languages. Following up on a paper with a similar title, this paper focuses on dynamically typed languages, covering issues ranging from parsing to defining and staging an interpreter for an interesting subset of Dr. Scheme. Preliminary experimental results indicate that the speedups reported in previous work for smaller languages and with smaller benchmarks are maintained. © 2008 Springer Berlin Heidelberg.
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| 4. |
- Taha, Walid, 1971-
(författare)
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Domain-Specific Languages
- 2008
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Ingår i: The 2008 International Conference on Computer Engineering & Systems (ICCES '08). - Piscataway, NJ : IEEE Press. - 9781424421152 - 9781424421169 ; , s. XXV-XXVIII
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- Recently, there has been a growing interest in what have come to be known as domain-specific languages (DSLs). This paper introduces a definition for DSLs, explains how DSLs can have a far-reaching impact on our lives, and discusses why DSLs are here to stay. © 2008 IEEE.
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