| 1. |
- Sentilles, Séverine, et al.
(författare)
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Save-IDE – A Tool for Design, Analysis andImplementation of Component-based Embedded Systems
- 2009
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Ingår i: 31st International Conference on Software Engineering(ICSE). - IEEE Computer Society. - 978-1-4244-3453-4 ; s. 607-610
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Konferensbidrag (refereegranskat)abstract
- The paper presents Save-IDE, an Integrated Development Environment for thedevelopment of component-based embedded systems. Save-IDE supports efficient development of dependable embedded systems by providing tools for design of embedded software systems using a dedicated component model, formal specification and analysis of component and system behaviors already in early development phases, and a fully automated transformation of the system of components into an executable image.
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| 2. |
- Åkerholm, Mikael, et al.
(författare)
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Handling Subsystems using the SaveComp Component Technology
- 2006
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Ingår i: Workshop on Models and Analysis for Automotive Systems (WMAAS'06) in conjunction with the 27th IEEE Real-Time Systems Symposium (RTSS'06), Rio de Janeiro, Brazil.
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Konferensbidrag (refereegranskat)
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| 3. |
- Åsberg, Mikael, et al.
(författare)
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Modelling, Verification and Synthesis of Two-Tier Hierarchical Fixed-Priority Preemptive Scheduling
- 2011
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Ingår i: Proceedings - 23rd EUROMICRO Conference on Real-Time Systems (ECRTS'11). - 9780769544427 ; s. 172-181
-
Konferensbidrag (refereegranskat)abstract
- Hierarchical scheduling has major benefits when it comes to integrating hard real-time applications. One of those benefits is that it gives a clear runtime separation of applications in the time domain. This in turn gives a protection against timing error propagation in between applications. However, these benefits rely on the assumption that the scheduler itself schedules applications correctly according to the scheduling parameters and the chosen scheduling policy. A faulty scheduler can affect all applications in a negative way. Hence, being able to guarantee that the scheduler is correct is of great importance. Therefore, in this paper, we study how properties of hierarchical scheduling can be verified. We model a hierarchically scheduled system using task automata, and we conduct verification with model checking using the Times tool. Further, we generate C-code from the model and we execute the hierarchical scheduler in the Vx Works kernel. The CPU and memory overhead of the modelled scheduler is compared against an equivalent manually coded two-level hierarchical scheduler. We show that the worst-case memory consumption is similar and that there is a considerable difference in CPU overhead.
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| 4. |
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