| 1. |
- Abbasi, Morteza, 1982, et al.
(författare)
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A 80-95 GHz direct quadrature modulator in SiGe technology
- 2014
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Ingår i: SiRF 2014 - 2014 IEEE 14th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems. - 9781479915231 ; , s. 56-58
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Konferensbidrag (refereegranskat)abstract
- A direct carrier IQ modulator operating in the 80-95 GHz frequency range is presented. The circuit is designed and fabricated in 0.18μm SiGe technology with 170/250 GHz fT/fmax. The modulator is based on double-balanced gilbert mixer cells with on-chip quadrature LO phase shifter and consumes 23mW DC power. In single-sideband operation, the chip exhibits up to 3 dB conversion gain below 85 GHz and -1± 0.5 dB up to 95 GHz. The image rejection ratio and LO-RF isolation are as high as 25 dB and 43 dB respectively. The modulator can operate with 10 GHz of modulation bandwidth and delivers -7 dBm power in saturation. For demonstration, the circuit is tested and shown to be capable of transmitting 4Gbps BPSK signal with NRZ rectangular pulses. The active chip area is 480μm× 260μm. © 2014 IEEE.
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| 2. |
- Abbasi, Morteza, 1982, et al.
(författare)
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A Broadband 60-to-120 GHz single-chip MMIC multiplier chain
- 2009
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Ingår i: IEEE MTT-S International Microwave Symposium Digest. - 0149-645X. ; , s. 441-444
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Konferensbidrag (refereegranskat)abstract
- This paper presents a single-chip 60 GHz to 120 GHz frequency multiplier chain based on 0.1 ?m GaAs mHEMT. The MMIC can deliver 3 to 5 dBm of output power from 110 GHz to 130 GHz with 2 dBm input power and consumes only 65 mW of DC power. The signal at the fundamental frequency is suppressed more than 20 dB over the band of interest. The impedance matching networks are realized using coupled transmission lines.
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| 3. |
- Abbasi, Morteza, 1982, et al.
(författare)
-
A broadband differential cascode power amplifier in 45 nm CMOS for high-speed 60 GHz system-on-chip
- 2010
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Ingår i: 2010 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2010; Anaheim, CA; 23 May 2010 through 25 May 2010. - 1529-2517. ; , s. 978-142446242-1-
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Konferensbidrag (refereegranskat)abstract
- A compact two-stage differential cascode power amplifier is designed and fabricated in 45 nm standard LP CMOS. The cascode configuration, with the common gate device placed in a separate P-well, provides reliable operating condition for the devices. The amplifier shows 20 dB small-signal gain centered at 60 GHz with a flat frequency response and 1-dB bandwidth of 10 GHz. The broadband large-signal operation is also ensured by providing constant load resistance to both stages over the entire band and coupling them with a dual resonance matching network. The chip delivers 11.2 dBm output power at 1-dB compression and up to 14.5 dBm power in saturation. The power amplifier operates with 2 V supply and draws 90 mA total current which results in 14.4% maximum PAE. The output third order intercept point is measured to be 18 dBm for two-tone measurement at 60 GHz with 0.5 GHz, 1 GHz and 2 GHz frequency separations. © 2010 IEEE.
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| 4. |
- Abbasi, Morteza, 1982, et al.
(författare)
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A direct conversion quadrature transmitter with digital interface in 45 nm CMOS for high-speed 60 GHz communications
- 2011
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Ingår i: Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium. Baltimore, 5-7 June 2011. - 1529-2517. - 9781424482931
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Konferensbidrag (refereegranskat)abstract
- A compact 60 GHz direct conversion quadrature transmitter is designed and fabricated in 45 nm standard LP CMOS. The transmitter features an integrated power amplifier with continuous output level control and interfaces binary data signals with nominal peak-to-peak voltage swing of 300 mV. The highest measured modulation bandwidth is limited by the measurement setup to 4 GHz but is simulated to be as high as 10 GHz. In single sideband up-converting operation mode, the measured image suppression ratio is 22 dB with 36 dB of carrier suppression corresponding to approximately 8% EVM in the output signal constellation. The output RF frequency can be from 54 GHz to 66 GHz to accommodate several channels and the output power can be adjusted from -3 dBm to 10 dBm. The chip is operated from a 2 V supply and draws 180 mA current.
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| 5. |
- Abbasi, Morteza, 1982, et al.
(författare)
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Single-Chip 220-GHz Active Heterodyne Receiver and Transmitter MMICs With On-Chip Integrated Antenna
- 2011
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Ingår i: IEEE Transactions on Microwave Theory and Techniques. - 0018-9480 .- 1557-9670. ; 59:2, s. 466-478
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents the design and characterization of single-chip 220-GHz heterodyne receiver (RX) and transmitter (TX) monolithic microwave integrated circuits (MMICs) with integrated antennas fabricated in 0.1-mu m GaAs metamorphic high electron-mobility transistor technology. The MMIC receiver consists of a modified square-slot antenna, a three-stage low-noise amplifier, and a sub-harmonically pumped resistive mixer with on-chip local oscillator frequency multiplication chain. The transmitter chip is the dual of the receiver chip by inverting the direction of the RF amplifier. The chips are mounted on 5-mm silicon lenses in order to interface the antenna to the free space and are packaged into two separate modules. The double-sideband noise figure (NF) and conversion gain of the receiver module are measured with the Y-factor method. The total noise temperature of 1310 +/- 100K(corresponding to an NF of 7.4 dB), including the losses in the lens and antenna, is measured at 220 GHz with a respective conversion gain of 3.5 dB. The radiated continuous-wave power from the transmitter module is measured to be up to -6 dBm from 212 to 226 GHz. The transmitter and receiver are linked in a quasi-optical setup and the IF to IF response is measured to be flat up to 10 GHz. This is verified to be usable for transmission of a 12.5-Gb/s data stream between the transmit and receive modules over a 0.5-m wireless link. The modules operate with a 1.3-V supply and each consume 110-mW dc power. The presented 220-GHz integrated circuits and modules can be used in a variety of applications, including passive and active imaging, as well as high-speed data communications. To the best of our knowledge, these MMICs are the highest frequency single-chip low-noise heterodyne receiver and transmitter pair reported to date.
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| 6. |
- Abbasi, Morteza, 1982, et al.
(författare)
-
Single-Chip Frequency Multiplier Chains for Millimeter-Wave Signal Generation
- 2009
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Ingår i: IEEE Transactions on Microwave Theory and Techniques. - 0018-9480 .- 1557-9670. ; 57:12, s. 3134-3142
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Tidskriftsartikel (refereegranskat)abstract
- Two single-chip frequency multiplier chains targeting 118 and 183 GHz output frequencies are presented. The chips are fabricated in a 0.1 mu m GaAs metamorphic high electron-mobility transistor process. The D-band frequency doubler chain covers 110 to 130 GHz with peak output power of 5 dBm. The chip requires 2 dBm input power and consumes only 65 mW of dc power. The signal at the fundamental frequency is suppressed more than 25 dB compared to the desired output signal over the band of interest. The G-band frequency sextupler (x6) chain covers 155 to 195 GHz with 0 dBm peak output power and requires 6.5 dBm input power and 92.5 mW dc power. The input signal to the multiplier chain can be reduced to 4 dBm while the output power drops only by 0.5 dB. The unwanted harmonics are suppressed more than 30 dB compared to the desired signal. An additional 183 GHz power amplifier is presented to be used after the x6 frequency multiplier chain if higher output power is required. The amplifier delivers 5 dBm output power with a small-signal gain of 9 dB from 155 to 195 GHz. The impedance matching networks are realized using coupled transmission lines which is shown to be a scalable and straightforward structure to use in amplifier design. Microstrip transmission lines are used in all the designs.
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| 7. |
- An, Sining, 1991, et al.
(författare)
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A 40 Gbps DQPSK Modem for Millimeter-wave Communications
- 2016
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Ingår i: Asia-Pacific Microwave Conference Proceedings APMC 2015. ; 1
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Konferensbidrag (refereegranskat)abstract
- A high speed differential quadrature phase shift keying (DQPSK) modulator and demodulator (modem) is presented for data rates up to 40 Gbps, in which the modulator is based on an FPGA and the demodulator is based on analog components. The modem performance has been verified in a lab environment. The targeted application is wireless communications using millimeter-wave bands as a flexible alternative to optical fiber links in next generation mobile networks.
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| 8. |
- An, Sining, 1991, et al.
(författare)
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A D-band Dual-Mode Dynamic Frequency Divider in 130nm SiGe Technology
- 2020
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Ingår i: IEEE Microwave and Wireless Components Letters. - 1558-1764 .- 1531-1309. ; 30:12, s. 1169-1172
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Tidskriftsartikel (refereegranskat)abstract
- In this work, a dual-mode (divide-by-2 and divide-by-3) dynamic frequency divider is presented. A tunable delay gated ring oscillator (TDGRO) topology is proposed for dual-mode operation and bandwidth extension. It uses a 130 nm gate length SiGe BiCMOS technology with ft and fmax of 250 GHz and 370 GHz, respectively. Verification shows that it works at W-band from 70 GHz to 114 GHz (47.8% bandwidth) for divide-by-2 and works at D-band from 105 GHz to 160 GHz (41.5% bandwidth) for divide-by-3. This divider can be used in integrated phase lock loops (PLLs) at millimeter-wave frequencies.
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| 9. |
- An, Sining, 1991, et al.
(författare)
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A Synchronous Baseband Receiver for High-Data-Rate Millimeter-Wave Communication Systems
- 2019
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Ingår i: IEEE Microwave and Wireless Components Letters. - 1558-1764 .- 1531-1309. ; 29:6, s. 412-414
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Tidskriftsartikel (refereegranskat)abstract
- A novel synchronous baseband receiver is presented in this letter. With a pilot tone insertion at the transmitter, the proposed baseband receiver can perform carrier recovery (CR) regardless of modulation scheme and/or baud rate. The synchronous baseband receiver has an analog-digital hybrid structure, where a low-cost digital signal processor controls an analog local oscillator (LO) in frequency and phase to achieve CR. This structure requires only one low-cost analog-to-digital converter (ADC) with a sampling rate of 100 MS/s. A proof-of-concept demonstration at E-band achieves 9-Gb/s 64-quadratic-amplitude modulation (QAM) and 16-Gb/s QPSK transmissions.
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| 10. |
- An, Sining, 1991, et al.
(författare)
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An 8 Gbps E-band QAM Transmitter Using Symbol-based Outphasing Power Combining Technique
- 2017
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Ingår i: Radio-Frequency Integration Technology (RFIT2017). - 9781509040360 ; , s. 150-152
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Konferensbidrag (refereegranskat)abstract
- In millimeter-wave communication systems, generating high output power with high efficiency on the transmitter side is one major challenge. In this paper, a symbol-based outphasing power combining solution has been demonstrated with data rate up to 8 Gbps at an RF frequency of 83.5 GHz. This solution provides 2 dB higher output power compared to the power of two QAM signals at 12% EVM.
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