| 1. |
- Agirre, J. A., et al.
(författare)
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The VALU3S ECSEL project : Verification and validation of automated systems safety and security
- 2021
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Ingår i: Microprocessors and microsystems. - : Elsevier BV. - 0141-9331 .- 1872-9436. ; 87, s. 104349-
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Tidskriftsartikel (refereegranskat)abstract
- Manufacturers of automated systems and their components have been allocating an enormous amount of time and effort in R&D activities, which led to the availability of prototypes demonstrating new capabilities as well as the introduction of such systems to the market within different domains. Manufacturers need to make sure that the systems function in the intended way and according to specifications. This is not a trivial task as system complexity rises dramatically the more integrated and interconnected these systems become with the addition of automated functionality and features to them. This effort translates into an overhead on the V&V (verification and validation) process making it time-consuming and costly. In this paper, we present VALU3S, an ECSEL JU (joint undertaking) project that aims to evaluate the state-of-the-art V&V methods and tools, and design a multi-domain framework to create a clear structure around the components and elements needed to conduct the V&V process. The main expected benefit of the framework is to reduce time and cost needed to verify and validate automated systems with respect to safety, cyber-security, and privacy requirements. This is done through identification and classification of evaluation methods, tools, environments and concepts for V&V of automated systems with respect to the mentioned requirements. VALU3S will provide guidelines to the V&V community including engineers and researchers on how the V&V of automated systems could be improved considering the cost, time and effort of conducting V&V processes. To this end, VALU3S brings together a consortium with partners from 10 different countries, amounting to a mix of 25 industrial partners, 6 leading research institutes, and 10 universities to reach the project goal.
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| 2. |
- Fakih, Maher, et al.
(författare)
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Experimental Evaluation of SAFEPOWER Architecture for Safe and Power-Efficient Mixed-Criticality Systems
- 2019
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Ingår i: Journal of Low Power Electronics and Applications. - : MDPI AG. - 2079-9268. ; 9:1
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Tidskriftsartikel (refereegranskat)abstract
- With the ever-increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible. Even in safety-critical domains like railway and avionics, multicore processors are introduced, but under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such a System on Chip (SoC) is to enhance the way the SoC handles its power consumption. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC, which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power-saving methods in safety-critical domains yet. The EU project SAFEPOWER (Safe and secure mixed-criticality systems with low power requirements) targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality systems. This article provides an overview of the SAFEPOWER reference architecture for low-power mixed-criticality systems, which is the most important outcome of the project. Furthermore, the application of this reference architecture in novel railway interlocking and flight controller avionic systems was demonstrated, showing the capability to achieve power savings up to 37%, while still guaranteeing time-triggered task execution and time-triggered NoC-based communication.
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| 3. |
- Fakih, M., et al.
(författare)
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SAFEPOWER project : Architecture for safe and power-efficient mixed-criticality systems
- 2017
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Ingår i: Microprocessors and microsystems. - : Elsevier. - 0141-9331 .- 1872-9436. ; 52, s. 89-105
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Tidskriftsartikel (refereegranskat)abstract
- With the ever increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible without regarding their criticality. Even safety critical domains like railway and avionics apply these paradigms under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such System on Chip (SoC) is to enhance the way the SoC handles its power resources. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power saving methods in safety critical domains yet. The EU project SAFEPOWER1.
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| 4. |
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| 5. |
- Pamunuwa, Dinesh, et al.
(författare)
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A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime
- 2004
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Ingår i: Integration. - : Elsevier BV. - 0167-9260 .- 1872-7522. ; 38:1, s. 3-17
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Tidskriftsartikel (refereegranskat)abstract
- On-chip packet-switched networks have been proposed for future giga-scale integration in the nanometre regime. This paper examines likely architectures for such networks and considers trade-offs in the layout, performance, and power consumption based on full-swing, voltage-mode CMOS signalling. A study is carried out for a future technology with parameters as predicted by the International Technology Roadmap for Semiconductors to yield a quantitative comparison of the performance and power trade-off for the network. Important physical level issues are discussed.
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| 6. |
- Öberg, Johnny, et al.
(författare)
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Grammar-based design of embedded systems
- 2001
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Ingår i: Journal of systems architecture. - : Elsevier. - 1383-7621 .- 1873-6165. ; 47:3-4, s. 225-240
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Tidskriftsartikel (refereegranskat)abstract
- Grammars define syntax of languages and as such have not been commonly considered as methods for design, despite well-known applications in computer science. Only in recent years grammar-based design has become a promising research field and the first commercial tools have appeared on the market. This paper reviews the basic concepts of applying grammars to electronic design - in particular to the device driver synthesis of communication protocols for embedded software, to the design of custom-hardware, and to the virtual prototyping of DSP systems. The paper shows the power of these methods, presents the latest research results and discusses future developments in this field.
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| 7. |
- Öberg, Johnny, et al.
(författare)
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Grammar-based hardware synthesis from port-size independent specifications
- 2000
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Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. - : Institute of Electrical and Electronics Engineers (IEEE). - 1063-8210 .- 1557-9999. ; 8:2, s. 184-194
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Tidskriftsartikel (refereegranskat)abstract
- A protocol defines how systems communicate. There are two ways of specifying the protocol, the language of communication. One way is to specify the automaton that recognizes the language, and this is the approach taken by SDL, etc. The other more abstract way ss to specify the grammar of the language and let a tool synthesize the automaton. Directly specifying the automaton makes the specification implementation dependent in two ways: the time behavior is specified in terms of states, and the width of the inputs and outputs is fixed. By specifying the grammar, the specification is potentially independent of both these implementation details and allows design space exploration in these dimensions. This paper presents a grammar-based language, called Program, that supports a port-size independent specifications methodology and its application to parts of the Operation and Maintenance protocol, a typical application from the ATM world. The methodology has also been applied to another test set of example designs and compared to standard RTL synthesis and HLS in order to evaluate the quality of the produced designs.
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| 8. |
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