| 1. |
- Isoaho, Jouni, et al.
(författare)
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High level synthesis in DSP ASIC optimization
- 1994
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Ingår i: Proc. of 7th IEEE ASIC Conference and Exhibit. ; , s. 75-78
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Konferensbidrag (refereegranskat)abstract
- In this paper Digital Signal Processing (DSP) system optimization with High Level Synthesis (HLS) environment is presented. To optimize a behavioural VHDL description, commercial SYNT and Synopsys synthesis tools are utilized. The optimization results are improved with a simple rule based preallocator. The coefficient optimization is done in Matlab to provide an efficient implementation of power-of-two and multiply-accumulate based FIR filters. The optimization results are presented using practical filter examples
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| 2. |
- Isoaho, Jouni, et al.
(författare)
-
HLS based DSP optimization with ASIC RTL libraries
- 1994
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Ingår i: ; , s. 218-225
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Konferensbidrag (refereegranskat)abstract
- In this paper we show how the High Level Synthesis (HLS) tool can efficiently be used for DSP ASIC development. The performance of general HLS tool is improved with simple transformations and code optimizations, and a direct mapping to technology optimized parameterizable ASIC Register Transfer Level (RTL) library. The library mapping contains three phases: a structure recognition, an architecture selection and a parameter optimization. As an optimization framework SYNT, Synopsys and Matlab design environments are integrated. Lsi10k and Xilinx 4000 series are used as target technologies to demonstrate the performance of the approach
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| 3. |
- Öberg, Johnny, et al.
(författare)
-
A rule-based approach for improving allocation of filter structures in HLS
- 1996
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Ingår i: Ninth International Conference on VLSI Design, 1996. Proceedings. - : IEEE conference proceedings. - 0818672285 ; , s. 133-139
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Konferensbidrag (refereegranskat)abstract
- A rule based allocator for improving synthesis of filter systems is presented. The principles of the Enhanced AIlocation Rule Language Interpreter (EARLI) are presented. Possible transformations, optimisations and how to express them in EARLI are discussed. Experiments show that relative area gains ranging from 5 to 44%, depending on the chosen target technology, can be achieved using the designers knowledge about the design class. Experiments also indicate that employing direct mapping of CDFG subgraphs onto preoptimised RTL-level macroblocks would have resulted in a relative area gain of 500%. The macroblock had only 16% of the area produced by the HLS-tool
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