| 1. |
- Deb, Abhijit Kumar, et al.
(författare)
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Hardware software codesign of DSP system using grammar based approach
- 2001
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Ingår i: VLSI Design, 2001. Fourteenth International Conference on. ; , s. 42-47
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Konferensbidrag (refereegranskat)abstract
- Embedded cores are gaining widespread use to deal with the complex DSP systems where flexibility is of utmost importance. The design of such a system offers several problems, which are not addressed by the existing methodology. The authors previously presented an integrated grammar based DSP design methodology that separates architectural and functional specification, can create a virtual prototype and has a smooth link to the implementation phase. In this paper we present the extension of the work to handle embedded cores. Here we the capture the host peripheral interface (HPI) of TMS320C6x core at higher level of abstraction and provide a single simulation environment, which facilitates faster analysis of hardware software components. Our results reveal that the proposed methodology offers simulation time speed-up of 5 times and design time speed-up of 8 times, while keeping the architectural specification separated from functionality
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| 2. |
- Hemani, Ahmed, et al.
(författare)
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Lowering power consumption in clock by using globally asynchronous locally synchronous design style
- 1999
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Ingår i: Design Automation Conference, 1999. Proceedings. 36th. ; , s. 873-878
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Konferensbidrag (refereegranskat)abstract
- Power consumption in clock of large high performance VLSIs can be reduced by adopting globally asynchronous, locally synchronous design style (GALS). GALS has small overheads for the global asynchronous communication and local clock generation. We propose methods to (a) evaluate the benefits of GALS and account for its overheads, which can be used as the basis for partitioning the system into optimal number/size of synchronous blocks, and (b) automate the synthesis of the global asynchronous communication. Three realistic ASICs, ranging in complexity from 1 to 3 million gates, were used to evaluate GALS benefits and overheads. The results show an average power saving of about 70% in clock with negligible overheads
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| 3. |
- Hemani, Ahmed, et al.
(författare)
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Lowering Power Consumption in Clock by Using Globally Asynchronous Locally Synchronous Design Style
- 1999
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Ingår i: Proceedings of the 36th ACM/IEEE conference on Design automation. - New York, NY, USA : ACM. ; , s. 873-878
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Konferensbidrag (refereegranskat)abstract
- Power consumption in clock of large high performance VLSIs can be reduced by adopting Globally Asynchronous, Locally Synchronous design style (GALS). GALS has small overheads for the global asynchronous communication and local clock generation. We propose methods to a) evaluate the benefits of GALS and account for its overheads, which can be used as the basis for partitioning the system into optimal number/size of synchronous blocks, and b) automate the synthesis of the global asynchronous communication. Three realistic ASICs, ranging in complexity from 1 to 3 million gates, were used to evaluate GALS benefits and overheads. The results show an average power saving of about 70% in clock with negligible overheads.
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| 4. |
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| 5. |
- Hemani, Ahmed, et al.
(författare)
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System level virtual prototyping of DSP ASICs using grammar based approach
- 1999
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Ingår i: Rapid System Prototyping, 1999. IEEE International Workshop on. ; , s. 166-171
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Konferensbidrag (refereegranskat)abstract
- DSP systems are often modeled using functional and bit-true level simulators, where it is not possible to validate the system level timing, control and configuration (SLTCC) of the product. In this paper, we present a methodology that adds SLTCC specified in grammar to functional models to create a rate true system level virtual prototype. The methodology is illustrated and benefits are quantified using two realistic examples
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| 6. |
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| 7. |
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| 8. |
- Meincke, Thomas, et al.
(författare)
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Globally asynchronous locally synchronous architecture for large high-performance ASICs
- 1999
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Ingår i: ; 2, s. 512-515
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Konferensbidrag (refereegranskat)abstract
- Clock nets are the major source of power consumption in large, high-performance ASICs and a design bottleneck when it comes to tolerable clock skew. A way to obviate the global clock net is to partition the design into large synchronous blocks each having its own clock. Data with other blocks is exchanged asynchronously using handshake signals. Adopting such a strategy requires a methodology that supports: 1) a partitioning method dividing a design into the number of synchronous blocks such that the gain due to global clock net removal exceeds the communication overhead and 2) synthesis of handshake protocols to implement the data transfer between synchronous blocks. We describe this methodology and present results of applying it to a realistic design done in 0.25 micron, ranging in operating frequencies from 20 MHz to 1 GHz. The results show that the net power savings compared to fully synchronous designs are on an average about 30%
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